New Taipei, Taiwan

Chieh-Ming Chang

This inventor holds 1 USPTO granted patent and 3 published patent applications. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chieh-Ming Chang. Retrieved from https://idiyas.com/inventor/chieh-ming-chang-3ye1n24b

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Chieh-Ming Chang and Semiconductor Package Innovation.

Introduction.

Chieh-Ming Chang is an inventor based in New Taipei, Taiwan. His listed patent work concerns semiconductor packaging, with a design that combines a protective cover and a stiffener structure.

Latest Patents.

Chang is associated with 1 patent, titled “Semiconductor Package with Stiffener Structure.” The patent describes a chip package containing a semiconductor die mounted over a package substrate and an interconnect structure electrically connecting the die to the substrate. A metal stiffener covers the die and includes a lid cap over its upper surface, a surrounding ring, and a spacer wall extending between the ring and the substrate. Together, these components surround and cover the die.

Career Highlights.

Chang is associated with Taiwan Semiconductor Manufacturing Company Limited. His listed patent reflects work in semiconductor packaging, where structural support and protection are integrated into the package design.

Collaborations.

The patent describes a package structure involving a semiconductor die, package substrate, interconnect structure, and metal stiffener. The available information does not identify additional collaborators or specify their individual contributions.

Conclusion.

Chieh-Ming Chang’s listed patent focuses on a stiffened semiconductor package that covers and surrounds a die, highlighting his contribution to semiconductor packaging innovation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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