Taichung City, Taiwan

Chieh-Lung Lai

This inventor holds 2 USPTO granted patents and 3 published patent applications. Top assignee: Taiwan Semiconductor Manufacturing Co., Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chieh-Lung Lai. Retrieved from https://idiyas.com/inventor/chieh-lung-lai-kje2yuzg

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 2 

Average Co-Inventor Count = 5.0


Company Filing History:


Years Active: 2026

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2 patents (USPTO):Explore Patents

Title: Chieh-Lung Lai and Integrated Circuit Packaging

Introduction

Chieh-Lung Lai is an inventor associated with Taichung City, Taiwan. His patent work concerns integrated circuit packaging, including interposer structures and methods for forming them.

Latest Patents

The provided information lists 1 patent for Lai: “Integrated Circuit Packages and Methods of Forming the Same.” The invention describes an integrated circuit package with an interposer containing multiple redistribution layers. In its central region, a second redistribution layer sits above a first redistribution layer, while a dielectric layer covers the first redistribution layer in the periphery and surrounds the second redistribution layer when viewed from above. A third redistribution layer extends over the second redistribution layer and the dielectric layer. A direct via passes through the dielectric layer, connecting a conductive feature in the third redistribution layer to a conductive feature in the first redistribution layer.

Career Highlights

Lai is associated with Taiwan Semiconductor Manufacturing Co., Ltd. His listed patent focuses on interposer design and electrical connections within integrated circuit packages.

Collaborations

The provided information identifies Hsien-Wei Chen and Meng-Liang Lin as Lai’s coworkers.

Conclusion

Chieh-Lung Lai’s listed invention addresses integrated circuit packaging through a layered interposer design and a direct-via connection between redistribution layers.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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