Tainan, Taiwan

Chia-Chen Tsai

This inventor holds 4 USPTO granted patents. Top assignee: United Microelectronics Corp.. Active years: 2017-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chia-Chen Tsai. Retrieved from https://idiyas.com/inventor/chia-chen-tsai-x11dr5o6

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 4.4

ph-index = 1

Forward Citations = 6(Granted Patents)


Company Filing History:


Years Active: 2017-2025

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4 patents (USPTO):Explore Patents

Title: Chia-Chen Tsai: Innovator in Semiconductor Technology

Introduction

Chia-Chen Tsai is a prominent inventor based in Tainan, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 4 patents. His work focuses on innovative structures and manufacturing methods that enhance semiconductor devices.

Latest Patents

One of his latest patents is titled "NMOS structure and manufacturing method thereof." This patent describes an NMOS structure that includes a semiconductor substrate, a dielectric structure, a source doped region, a drain doped region, a channel region, a gate structure, and two isolation P-type wells. The dielectric structure is formed in the semiconductor substrate to define an active region, where the source/drain doped region and the channel region are formed. The channel region features two opposite first sides and two opposite second sides. The source/drain doped region is formed between the two second sides and the dielectric structure. The gate structure is positioned on the semiconductor substrate, covering part of the dielectric structure adjacent to the first sides. The two isolation P-type wells are created in the dielectric structure not covered by the gate structure, surrounding the periphery of the source/drain doped region and ending at the respective second side.

Another significant patent is the "Manufacturing method of semiconductor device." This method outlines the steps for creating a semiconductor device, starting with the formation of first and second gate structures on different regions of a semiconductor substrate. The spacing distance between the second gate structures is larger than that between the first gate structures. A first ion implantation is performed to create a first doped region between the first gate structures, followed by a second ion implantation to form a second doped region between the second gate structures. The tilt angle of the second ion implantation is greater than that of the first, and its implantation dose is lower. An etching process is then conducted to partially remove both doped regions, resulting in the formation of recesses.

Career Highlights

Chia-Chen Tsai is currently employed at United Microelectronics Corporation, a leading company in the semiconductor industry. His work has been instrumental in advancing semiconductor technology and improving device performance.

Collaborations

He collaborates with notable colleagues, including Ta-Kang Lo and Hung-Chang Chang, who contribute to his innovative projects and research efforts.

Conclusion

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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