United Microelectronics Corp.

Chia-Chen Tsai

Ta-Kang Lo

Tsai-Fu Chen

Hung-Chang Chang

Shang-Jr Chen

Shou-Wei Hsieh

Hau-Yuan Huang

Hsueh-Chih Tseng

Jia-Bin Yeh

Jiun-Lin Yeh

An NMOS structure includes a semiconductor substrate, a dielectric structure, a source doped region, a drain doped region, a channel region, a gate structure and two isolation P-type wells. The dielectric structure is formed in the semiconductor substrate to define an active region, in which the source/drain doped region and the channel region are formed. The channel region includes two opposite first sides and two opposite second sides. The source/drain doped region is respectively formed between the two second sides and the dielectric structure. The gate structure is formed on the semiconductor substrate. The gate structure covers a part of the dielectric structure beside the first sides. The two isolation P-type wells are formed in a part of the dielectric structure not covered by the gate structure. The isolation P-type wells respectively surround a periphery of the source/drain doped region and end at the respective second side.

NMOS structure and manufacturing method thereof

A manufacturing method of a semiconductor device includes following steps. First gate structures and second gate structures are formed on a first region and a second region of a semiconductor substrate respectively. A spacing distance between the second gate structures is larger than that between the first gate structures. A first ion implantation is preformed to form a first doped region between the first gate structures. A second ion implantation is performed to form a second doped region between the second gate structures. A tilt angle of the second ion implantation is larger than that of the first ion implantation. An implantation dose of the second ion implantation is lower than that of the first ion implantation. An etching process is performed to at least partially remove the first doped region to form a first recess and at least partially remove the second doped region to form a second recess.

Manufacturing method of semiconductor device

A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

Semiconductor device and method of manufacturing the same

A semiconductor device and method of manufacturing the same are provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

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Tainan, Taiwan

Chia-Chen Tsai