The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2017
Filed:
Feb. 29, 2016
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Chia-Chen Tsai, Tainan, TW;
Hung-Chang Chang, Taichung, TW;
Ta-Kang Lo, Taoyuan, TW;
Tsai-Fu Chen, Hsinchu, TW;
Shang-Jr Chen, Tainan, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/08 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 21/311 (2006.01); H01L 29/66 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/31144 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 29/165 (2013.01); H01L 29/6656 (2013.01); H01L 29/66636 (2013.01); H01L 29/7848 (2013.01);
Abstract
A semiconductor device and method of manufacturing the same are provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.