Taipei, Taiwan

Chi-Hsiang Chen

This inventor holds 1 USPTO granted patent and 2 published patent applications. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chi-Hsiang Chen. Retrieved from https://idiyas.com/inventor/chi-hsiang-chen-u5rfgd1k

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Chi-Hsiang Chen and Wafer-Level Die Transfer

Introduction

Chi-Hsiang Chen is an inventor based in Taipei, Taiwan, and is associated with Taiwan Semiconductor Manufacturing Company Limited. His patent work addresses wafer-level die transfer, a process relevant to handling and moving semiconductor dies.

Latest Patents

Chen is named on one patent, 1 patent: “Wafer-level die-transfer tool and method.” The invention describes a tool with source and target frame stages that secure separate tapes. The target tape’s adhesive surface faces the source stage, with multiple dies positioned between the tape and that adhesive surface. A roller moves laterally across the target tape’s non-adhesive side, while a driving mechanism adjusts the target stage’s vertical position relative to the source stage. Together, these components support the transfer of dies between tapes.

Career Highlights

The available information identifies Chen’s work with Taiwan Semiconductor Manufacturing Company Limited and highlights his contribution to semiconductor manufacturing through a patented die-transfer tool and method.

Collaborations

The patent information provided connects Chen with Taiwan Semiconductor Manufacturing Company Limited. No additional collaborators are specified in the supplied details.

Conclusion

Chi-Hsiang Chen’s patent focuses on a tool and method for transferring semiconductor dies at wafer level, combining controlled stage positioning with a laterally moving roller.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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