Chenwei Dustin Liu

Title: Chenwei Dustin Liu and Pattern-Based Static Timing Analysis.

Introduction

Chenwei Dustin Liu is an inventor based in Milpitas, California, and is associated with Synopsys, Inc. His patent work addresses methods for analyzing circuit timing, an important part of evaluating integrated circuit designs.

Latest Patents

Liu is credited with 1 patent: “Delay Calculation with Pattern Matching for Static Timing Analysis.” The invention describes identifying logic blocks in a circuit design that match a design pattern, determining electrical-property values for a representative block, and using those values to calculate delays for the matching blocks during static timing analysis.

Career Highlights

The patent reflects work on improving static timing analysis by applying representative electrical-property values across logic blocks with matching patterns. This approach connects circuit structure with delay calculation in the analysis of a design.

Collaborations

Liu’s listed company affiliation is Synopsys, Inc. His coworker Peivand Tehrani is identified as a woman. The available information does not specify her role in the patent.

Conclusion

Chenwei Dustin Liu’s patent focuses on pattern matching as a way to calculate circuit delays during static timing analysis, highlighting his contribution to electronic design automation.