The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 25, 2026
Filed:
Oct. 31, 2022
Applicant:
Synopsys, Inc., Sunnyvale, CA (US);
Inventors:
Peivand Tehrani, Campbell, CA (US);
Chenwei Dustin Liu, Milpitas, CA (US);
Ahmed Shebaita, Fremont, CA (US);
Assignee:
Synopsys, Inc., Sunnyvale, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3315 (2020.01); G06F 30/30 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3315 (2020.01); G06F 2119/12 (2020.01);
Abstract
A method of performing static timing analysis for a circuit design includes, in part, identifying a multitude of logic blocks of the circuit design matching a design pattern; determining values of a multitude of electrical properties associated with a first logic block representative of each of the plurality of logic blocks; and determining, during the static timing analysis, a delay associated with each of the multitude of logic blocks using the values of the electrical properties.