Chen-Sheng Lin

Title: Chen-Sheng Lin and Semiconductor Wafer-Trimming Innovation.

Introduction

Chen-Sheng Lin is an inventor based in Taoyuan City, Taiwan. His patent work includes a method for trimming a stacked wafer structure, addressing wafer-edge processing and surface leveling during semiconductor manufacturing.

Latest Patents

Lin is associated with 1 patent, titled “Trimming Method of Stacked Structure by Forming a Trench.” The method begins with a first wafer that has a thinner first portion and a thicker second portion. A second wafer is bonded to the first, and edge trimming forms a trench through the second wafer and into the second portion of the first wafer.

After dies are bonded to the second wafer, filling material is applied around and between the dies, over both wafers, and partly into the trench. The wafers are then thinned, removing the second portion and some of the filling material in the trench. This process brings the thinned wafer surface level with the surface of the thinned filling material.

Career Highlights

Lin is associated with Taiwan Semiconductor Manufacturing Company Limited. His patent describes a wafer-processing approach that combines edge trimming, die bonding, filling, and thinning in a stacked structure.

Collaborations

The provided information identifies Sheng-An Kuo and Eva Wang as Lin’s coworkers. No further details about their roles or specific contributions to the patent are available.

Conclusion

Chen-Sheng Lin’s patent focuses on trench-based edge trimming and surface leveling in stacked-wafer processing, reflecting an innovation relevant to semiconductor manufacturing.