Chen-Hsin Lien

Title: Innovations of Chen-Hsin Lien

Introduction

Chen-Hsin Lien is a prominent inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of three patents. His work focuses on improving the performance and efficiency of semiconductor devices.

Latest Patents

One of his latest patents is a method for fabricating a semiconductor device to lower source/drain sheet resistance. This method involves forming a dielectric layer with multiple contact windows on a semiconductor device, followed by selective epitaxial growth (SEG) and sputtering a metal layer. A silicide is then formed through heat treatment, ensuring that the silicon substrate remains intact and the depth of the junction region is preserved, ultimately lowering the source/drain sheet resistance. Another notable patent is the early triggered ESD MOSFET protection circuit and method. This invention describes a circuit that generates a transient negative voltage applied to the gate of a MOSFET during a positive ESD event, enhancing ESD performance, especially for thin gate oxides of 40 nm or less.

Career Highlights

Chen-Hsin Lien has worked with notable companies such as Winbond Electronics Corporation and the Industrial Technology Research Institute. His experience in these organizations has allowed him to develop innovative solutions in semiconductor technology.

Collaborations

Some of his coworkers include Shi-Tron Lin and Wei-Fan Chen. Their collaboration has contributed to the advancement of semiconductor research and development.

Conclusion

Chen-Hsin Lien's contributions to semiconductor technology through his patents and collaborations highlight his role as an influential inventor in the field. His innovative methods continue to impact the industry positively.