Winbond Electronics Corporation

Industrial Technology Research Institute

Chen-Hsin Lien

Shi-Tron Lin

Wei-Fan Chen

Ching-Yuan Ho

A method for fabricating a semiconductor device to lower source/drain sheet resistance is provided. A dielectric layer with a plurality of contact windows is formed on a semiconductor device. Next, selective epitaxial growth (SEG) is implemented, and then a metal layer is sputtered. After that, a silicide is formed by heat treatment. In another embodiment, selective epitaxial growth is implemented first, and then a dielectric layer with a plurality of contact windows is formed. Then, a metal layer is sputtered, and a silicide is then formed by heat treatment. Since the silicide is formed by way of SEG, the silicon substrate will not be consumed during the process of forming the silicide, and the depth of the junction region is maintained, and the source/drain sheet resistance is lowered.

Method for fabricating semiconductor device to lower source/drain sheet resistance

An early triggered MOSFET ESD protection circuit based on reduction of the trigger voltage is described. A transient negative voltage is generated and applied to a gate of a MOSFET during a positive ESD event. The instant invention improves ESD performance, and is particularly useful for thin gate oxide of 40 &#x212b; and less.

Early triggered ESD MOSFET protection circuit and method thereof

The present invention is directed to a semiconductor integrated circuit device having reduced leakage and the method of operating a semiconductor integrated circuit device with reduced leakage. The invention comprises an integrated circuit, including a passing transistor and a bias-application device coupled to the substrate of the passing transistor. The present invention has the passing transistor coupled to a storage cell. The bias-application device applies a first bias voltage of a positive value when the passing transistor is inactivated and applies a second bias voltage when the passing transistor is activated, wherein the second bias voltage is equal to or smaller than the first bias voltage. Further in accordance with the invention, there is provided a method of reducing the leakage of a passing transistor of N-type. The passing transistor is coupled with a storage cell. The method includes applying a first bias voltage of a positive value when the passing transistor is inactivated, and applying a second bias voltage when the passing transistor is activated, wherein the second bias voltage is equal to or smaller than the first bias voltage.

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Hsinchu, Taiwan

Chen-Hsin Lien