Fremont, CA, United States of America

Chaitanya Palusa

This inventor holds 25 USPTO granted patents and 2 published patent applications, primarily in SerDes Technology. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Avago Technologies General IP (Singapore) Pte. Ltd., Oracle International Corporation. Active years: 2013-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chaitanya Palusa. Retrieved from https://idiyas.com/inventor/chaitanya-palusa

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 25 

% Patents Active = 72.0

Average Co-Inventor Count = 4.4

ph-index = 7

Forward Citations = 149(Granted Patents)


Location History:

  • Fremont, CA (US) (2013 - 2023)
  • San Jose, CA (US) (2015 - 2024)

Company Filing History:


Years Active: 2013-2026

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Areas of Expertise:
SerDes Receiver
Adaptive Receiver
Multi-tap Equalizer
Clock Data Recovery
Inter-symbol Interference
Phase Detector
Baseline Wander Correction
Data Path
Frequency Calibration
Serializer-Deserializer
Jitter Injection
Feed Forward Equalization
25 patents (USPTO):Explore Patents

Title: The Innovative Mind of Chaitanya Palusa

Introduction

Chaitanya Palusa, a prominent inventor based in Fremont, CA, holds an impressive portfolio of 23 patents. His innovative contributions are particularly noticeable in the fields of digital communication and signal processing, reflecting a deep understanding of modern technological challenges.

Latest Patents

Chaitanya's latest innovations include two notable patents. The first is a "SerDes receiver with optimized CDR pulse shaping." This advanced system focuses on clock data recovery by incorporating a slicer that delivers an initial set of tentative decisions to a decision feedforward equalizer. This configuration aims to enhance the quality of the output signal through optimal pulse shaping to ensure the ideal location for sampling.

The second patent is for a "multi-tap decision feed-forward equalizer with precursor and postcursor taps." This configuration reduces noise and crosstalk by employing decision outputs from slicers as inputs to a finite impulse response (FIR) filter rather than relying on analog signal inputs. This innovation not only streamlines the equalization process but also lowers the bit-error rate (BER) of output decisions, boosting overall performance.

Career Highlights

Throughout his career, Chaitanya has made significant strides and has been associated with several leading technology companies. He has worked with Avago Technologies, Oracle International Corporation, and General IP (Singapore) Pte. Ltd. His diverse experiences across these firms have allowed him to refine his expertise in developing cutting-edge technologies and patents.

Collaborations

Chaitanya has had the opportunity to collaborate with leading minds in the industry, including esteemed professionals such as Adam Benjamin Healey and Tomasz Prokop. These collaborations have likely contributed to the depth and breadth of his patent portfolio and innovative thinking.

Conclusion

Chaitanya Palusa continues to push the boundaries of innovation in signal processing and communication technologies. With a proven record of impactful patents and collaborations, he remains a valuable asset to the tech community. His work not only enhances existing technologies but also lays the groundwork for future innovations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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