The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Feb. 10, 2014
Applicant:

Lsi Corporation, San Jose, CA (US);

Inventors:

Chaitanya Palusa, Fremont, CA (US);

Tomasz Prokop, Pleasanton, CA (US);

Hiep T. Pham, San Jose, CA (US);

Volodymyr Shvydun, Los Altos, CA (US);

Adam B. Healey, Newburyport, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/38 (2015.01); H04L 5/16 (2006.01); H04L 27/10 (2006.01); H04L 27/18 (2006.01); H04L 25/03 (2006.01); H04L 7/00 (2006.01); H04L 27/00 (2006.01); H04L 7/02 (2006.01); H03M 1/12 (2006.01); H03M 1/38 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03057 (2013.01); H04L 7/0087 (2013.01); H04L 7/02 (2013.01); H04L 25/03 (2013.01); H04L 27/0002 (2013.01); H03M 1/1215 (2013.01); H03M 1/38 (2013.01);
Abstract

Modular, low power serializer-deserializer receivers and methods for configuring such receivers are disclosed. The disclosed receivers are configured to sample input signals at the front-end utilizing a plurality of track-and-hold circuits time-interleaved based on a plurality of phase-shifted clock signals. The disclosed receivers are also modular and various processing components, including analog front-end and equalizers, are selectively utilized based on the determined length of the communication channel, ranging from ultra short reach applications to very short reach, medium reach, long reach and extra long reach applications.


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