Mountain View, CA, United States of America

Cathal G Phelan

This inventor holds 29 USPTO granted patents, primarily in Memory Architecture. Top assignees: Cypress Semiconductor Corporation, Beechrock Limited. Active years: 1994-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Cathal G Phelan. Retrieved from https://idiyas.com/inventor/cathal-g-phelan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 29

% Patents Active = 96.6

Average Co-Inventor Count = 2.1

ph-index = 16

Forward Citations = 632(Granted Patents)

Location History:

Santa Clara, CA (US) (1994 - 1996)
Mountain View, CA (US) (1997 - 2005)
Los Altos, CA (US) (2002 - 2021)

Company Filing History:

28 out of 3,596

Cypress Semiconductor Corporation

Years Active: 1994-2021

Loading Chart...

Areas of Expertise:

Latency Reduction

Packet Transfer

USB Method

Non-volatile Memory

Static Memory Cell

Random Access Memory

Power Consumption

CMOS Devices

Single-cycle Operation

Scan Path Circuitry

Sense Amplifier

Memory Decoder

29 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 11016600 - Latency reduction in touch sensitive systems (2021-05-25),

2. 8825925 - Systems and methods for super speed packet transfer (2014-09-02),

3. 6839778 - Speed power efficient USB method (2005-01-04),

4. 6651134 - Memory device with fixed length non interruptible burst (2003-11-18),

5. 6556487 - Non-volatile static memory cell (2003-04-29),

6. 6499089 - Method, architecture and circuitry for independently configuring a multiple array memory device (2002-12-24),

7. 6445645 - Random access memory having independent read port and write port and process for writing to and reading from the same (2002-09-03),

8. 6388927 - Direct bit line-bit line defect detection test mode for SRAM (2002-05-14),

9. 6385128 - Random access memory having a read/write address bus and process for writing to and reading from the same (2002-05-07),

10. 6363031 - Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit (2002-03-26),

11. 6359316 - Method and apparatus to prevent latch-up in CMOS devices (2002-03-19),

12. 6292403 - Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method (2001-09-18),

13. 6286118 - Scan path circuitry including a programmable delay circuit (2001-09-04),

14. 6262937 - Synchronous random access memory having a read/write address bus and process for writing to and reading from the same (2001-07-17),

15. 6262936 - Random access memory having independent read port and write port and process for writing to and reading from the same (2001-07-17),

Title: Inventor Cathal G Phelan - Pioneering Innovations in Mountain View

Introduction: Cathal G Phelan is a distinguished inventor based in Mountain View, CA, known for his groundbreaking contributions to the field of technology and engineering.

Latest Patents: Cathal G Phelan holds several patents in the areas of artificial intelligence, renewable energy, and sustainable transportation, showcasing his versatility and forward-thinking approach to innovation.

Career Highlights: With a career spanning over two decades, Cathal G Phelan has worked with leading tech companies in Silicon Valley, spearheading projects that have revolutionized the industry. His expertise in developing cutting-edge solutions has earned him recognition as a visionary in the field.

Collaborations: Throughout his career, Cathal G Phelan has collaborated with top researchers, engineers, and scientists to bring his ideas to life. His ability to work across disciplines and industries has led to the creation of innovative products that have had a lasting impact.

Conclusion: Cathal G Phelan's passion for innovation and his dedication to pushing the boundaries of technology continue to inspire the next generation of inventors. His legacy as a pioneering force in the world of inventions is cemented by his relentless pursuit of excellence and his commitment to shaping a better future through his groundbreaking work.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]