Cypress Semiconductor Corporation

Beechrock Limited

Cathal G Phelan

Ashish Pancholy

Jonathan F Churchill

Simon J Lovett

Neil P Raftery

Mark A Finn

Thomas M Surrette

Jeyakumar Shanmugam

Mathew R Arcoleo

Colin J Hendry

Christopher John Petti

Andrew J Walker

Owen Drumm

Ronald H Sartore

Steven Philip Larky

Hans Van Antwerpen

Gaurav Singh

Rajesh Manapat

Gary Austin Gibbs

Peter H Voss

Gregory J Landry

Sunil Kumar Koduru

Herve LeTourneur

Eric Wolf Gross

Nirmal Ratnakumar

Patrick Zicolello

Kenelm G D Murray

Scott Harmel

Kent M Kalpakjian

Jeffrey F Kooiman

Jeff Watt

A touch sensitive system includes a touch surface, a display, and a latency control system. The latency control system reduces the latency between a touch event occurring on the touch surface and a graphical response displayed by the display. Specifically, the latency control system is a feedback system that synchronizes touch scan and display operations. The touch scan and display operations are synchronized by adjusting timing parameters, such as the start times and frequencies of the scan and display operations. Thus, the latency control system is an adaptable system that may reduce latency even when the processing times of various operations vary over time.

Latency reduction in touch sensitive systems

An example method and system process a SuperSpeed packet transferred at a SuperSpeed transfer rate and based on processing the SuperSpeed packet, generate a Universal Serial Bus (USB) 2.0 packet to be transferred at a USB 2.0 transfer rate, the USB 2.0 transfer rate being less than the SuperSpeed transfer rate.

Systems and methods for super speed packet transfer

An apparatus comprising a peripheral device and a host device. The peripheral device may be connected to the host device. The speed of the peripheral device may be adjusted in response to one or more predetermined conditions.

Speed power efficient USB method

An integrated circuit comprising a memory and a logic circuit. The memory may comprise a plurality of storage elements each configured to read and write data in response to an internal address signal. The logic circuit may be configured to generate a predetermined number of the internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) one or more control signals. The generation of the predetermined number of internal address signals may be non-interruptible.

Memory device with fixed length non interruptible burst

A non-volatile SRAM cell including (i) a nonvolatile memory element, (ii) a volatile memory element coupled to the nonvolatile memory element and (iii) a gate circuit coupled to the nonvolatile memory element. The gate circuit is configured to transfer data to and from a first input/output line into the volatile memory element.

Non-volatile static memory cell

A circuit generally comprising a memory and a logic circuit. The memory may comprise (i) a first section configured to (a) read and write data and (b) have a first configurable size and (ii) a second section configured to (a) read and write data independently of the first section and (b) have a second configurable size. The logic circuit may be configured to control the first configurable size and the second configurable size.

Method, architecture and circuitry for independently configuring a multiple array memory device

A random access memory with a read port, a write port, a read/write control signal configured to control data transfer operations at the read port and/or the write port on both rising and falling transitions, and a first random access memory array configured to store and/or retrieve data at a first random address in the first random access memory array defined by one or more signals on a write address bus and/or a read address bus. One preferred embodiment further includes a write data register storing or latching data in response to a first transition of the read/write control signal, and the array storing data in response to a second transition of the read/write control signal. Other preferred embodiments further include an n&middot;m-bits-wide input data bus coupling a set of data inputs to the write data register, and/or an n&middot;m-bits-wide output data bus coupling the read data register to a set of data outputs, where n and m are each independently an integer >2.

Random access memory having independent read port and write port and process for writing to and reading from the same

A system and method are disclosed herein for leakage testing of a static random access memory (SRAM) semiconductor memory device. Subtle leakage defects may be present in some devices in the early stages of SRAM production. These defects may later result in hard failures when packaged devices are burned in, but are not detected by functional tests performed during wafer sort. The leakage defects are associated with complementary bit line pairs within the SRAM matrix, and may be revealed by leakage current measurements made between all of the complementary bit line pairs within the SRAM. Comparatively minor modifications to the internal circuitry of the SRAM enable the leakage measurements to be performed during wafer sort, so defective devices can be screened out prior to packaging, lead-bonding, etc.

Direct bit line-bit line defect detection test mode for SRAM

A random access memory with a data input bus, a data output bus, a random access memory array configured to transfer data to random write addresses and from random read addresses in the random access memory array, an address bus providing the random read addresses and the random write addresses, and a first periodic signal configured to control data transfer operations (i) to the random access memory array in response to a first transition of the periodic signal and (ii) from the random access memory array in response to a second transition of the periodic signal, wherein the second transition of the periodic signal is complementary to the first transition of the periodic signal. One preferred embodiment further includes circuitry operable to write data into and read data from the random access memory array. Other preferred embodiments further include a write data register and/or a read data register. In a further embodiment, each of the data input bus and the data output bus is unidirectional. The invention also concerns a process for reading data from and writing data to a random access memory array.

Random access memory having a read/write address bus and process for writing to and reading from the same

An apparatus comprising a circuit configured to automatically generate a sleep signal upon detecting that one or more chip select signals has been in a first state for a predetermined number of clock cycles.

Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit

A semiconductor (preferably a CMOS) device having one or more latch-up inhibitor diffusion regions. The latch-up inhibitor regions are adjacent to complementary P-channel and N-channel transistors, and typically function to inhibit or prevent latch-up, without increasing the die size of the device.

Method and apparatus to prevent latch-up in CMOS devices

A circuit including an address bus providing random addresses for a random access memory array, and a register configured to receive, store or transfer (i) a first random address from the address bus in response to a first periodic signal transition and (ii) a second random address from the address bus in response to a second periodic signal transition, wherein the first and second periodic signal transitions occur within a single periodic signal cycle, and are preferably complementary to each other. In a further embodiment, the invention concerns a random access memory having an address bus providing random address information for a random access memory array, a predecoder configured to at least partially decode the random address information from the address bus, a register configured to receive, store or transfer (i) a first at least partially decoded random address from the address bus in response to a first periodic signal transition and (ii) a second at least partially decoded random address from the address bus in response to a second periodic signal transition, wherein the first and second periodic signal transitions occur within a single periodic signal cycle; and a postdecoder configured to activate the random addresses in the random access memory in response to receiving the random addresses from the register.

Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method

A circuit for delaying a signal. The circuit includes a scan register, a logic circuit, and a programmable delay circuit. The scan register stores scan data and the logic circuit selectively decodes the scan data. The programmable delay circuit is coupled to the logic circuit and delays a signal a programmable amount of time in response to the decoded scan data.

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Mountain View, CA, United States of America

Cathal G Phelan