The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2002
Filed:
Sep. 19, 1997
Applicant:
Inventors:
Peter H. Voss, Watsonville, CA (US);
Andrew Walker, Mountain View, CA (US);
Jeff Watt, Mountain View, CA (US);
Ashish Pancholy, Milpitas, CA (US);
Cathal G. Phelan, Mountain View, CA (US);
Patrick Zicolello, Santa Clara, CA (US);
Christopher J. Petti, Menlo Park, CA (US);
Assignee:
Cypress Semiconductor Corp., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/976 ; H01L 2/710 ; H01L 2/994 ; H01L 3/1062 ;
U.S. Cl.
CPC ...
H01L 2/976 ; H01L 2/710 ; H01L 2/994 ; H01L 3/1062 ;
Abstract
A semiconductor (preferably a CMOS) device having one or more latch-up inhibitor diffusion regions. The latch-up inhibitor regions are adjacent to complementary P-channel and N-channel transistors, and typically function to inhibit or prevent latch-up, without increasing the die size of the device.