Singapore, Singapore

Cai Jun

This inventor holds 4 USPTO granted patents. Top assignee: Chartered Semiconductor Manufacturing Ltd (Corporation). Active years: 2001-2003.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Cai Jun. Retrieved from https://idiyas.com/inventor/cai-jun

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 75.0

Average Co-Inventor Count = 2.2

ph-index = 3

Forward Citations = 47(Granted Patents)


Company Filing History:


Years Active: 2001-2003

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4 patents (USPTO):Explore Patents

Title: Innovations of Inventor Cai Jun

Introduction

Cai Jun is a notable inventor based in Singapore, recognized for his contributions to the field of semiconductor technology. He holds a total of 4 patents, showcasing his innovative approach to electronic device protection.

Latest Patents

Cai Jun's latest patents include advancements in dummy layer diode structures for electrostatic discharge (ESD) protection. These structures feature a controllable dummy layer that provides a low controllable trigger voltage, serving as a first triggered device in ESD protection networks. The controllable dummy layer diode is designed as a butting diode with a dummy polysilicon layer above the butting region, which functions as an STI block to eliminate the STI between the n+ and p+ regions of the diode. This innovative design allows for adjustments in the reverse-biased voltage of the diode by modifying the channel length under the gate and the gate voltage.

Another significant patent involves a diode-like plasma induced damage protection (PID) device structure. This novel design includes an N-well, three associated N+ regions, and a P+ region formed on a P substrate. The diode-like PID protection device is structured as a butting diode with a polysilicon gate above the butting region. The gate connects to a metal antenna element and a zener-like trigger element, allowing the antenna to capture a portion of the plasma charge to provide a gate voltage. This design minimizes device leakage during normal IC operation by discharging any charge on the poly gate through the N-well resistor.

Career Highlights

Cai Jun is currently employed at Chartered Semiconductor Manufacturing Ltd, where he continues to innovate in the semiconductor industry. His work has significantly impacted the development of ESD protection technologies, enhancing the reliability of electronic devices.

Collaborations

Cai Jun has collaborated with notable colleagues, including Lo Keng Foo and Yao Pei, contributing to various projects that advance semiconductor technology.

Conclusion

Cai Jun's innovative patents and contributions to the semiconductor field highlight his expertise and commitment to enhancing electronic device protection. His work continues to influence the industry, paving the way for future advancements.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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