Chartered Semiconductor Manufacturing Ltd (corporation)

Cai Jun

Lo Keng Foo

Keng Foo Lo

He Can Zhong

Yao Pei

Described are structures for a device with a controllable dummy layer which can provide a low controllable trigger voltage and can be used as a first triggered device in ESD protection networks. A controllable dummy layer diode is provided which is structured as a butting diode with a dummy polysilicon layer above the butting region. The dummy polysilicon layer functions as an STI block to remove the STI between the n&plus; and p&plus; regions of the diode. In one embodiment the diode has the function of a controllable gate with a punchthrough-like-trigger, in which a capacitor-couple circuit couples a portion of the ESD voltage into the gate of the diode to provide a gate voltage. By changing the channel length under the gate of the diode as well as the gate voltage, the reverse-biased voltage of the diode is readily adjusted to a predetermined

Dummy layer diode structures for ESD protection

A novel structured for a diode-like PID protection (DLPP) device structure and process are described. An N-well, three associate N&plus; regions and a P&plus; region are formed on a P substrate. The DLPP is structured as a butting diode with a polysilicon gate above the butting region. The gate is connected to a metal antenna element and to the zener like trigger element of the device. The N-well functions as a resistor and capacitor buffer between the poly gate and antenna and the substrate. The antenna picks up a portion of the plasma charge to provide a gate voltage. There is an inversion layer or accumulation layer for positive or negative plasma charge formed under the poly gate. The junction of the effective zener diode is found in the interface between the N-type inversion layer and P&plus;, or N&plus; and P-type accumulation layer. Changing the shape and the size of the antenna changes the gate voltage, and subsequently the trigger voltage of the DLPP. During normal IC operation, any charge on the poly gate or associated antenna has been discharged through the N-well resistor and therefore no channel exists under the poly gate minimizing any device leakage. An alternative embodiment uses a N doped substrate with appropriately doped well and contact regions.

Diode-like plasma induced damage protection structure

Described are structures for a device with a controllable dummy layer which can provide a low controllable trigger voltage and can be used as a first triggered device in ESD protection networks. A controllable dummy layer diode is provided which is structured as a butting diode with a dummy polysilicon layer above the butting region. The dummy polysilicon layer functions as an STI block to remove the STI between the n&plus; and p&plus; regions of the diode. In one embodiment the diode has the function of a controllable gate with a punchthrough-like-trigger, in which a capacitor-couple circuit couples a portion of the ESD voltage into the gate of the diode to provide a gate voltage. By changing the channel length under the gate of the diode as well as the gate voltage, the reverse-biased voltage of the diode is readily adjusted to a predetermined level. In a second embodiment the p&plus; region of the diode overlaps the n&plus; region turning the diode into a zener diode. The low doping channel region under the dummy polysilicon layer functions as a channel stopper and suppresses the occurrence of the leakage current caused by the zener diode. The adjustment of the channel stopper length and the controllable gate voltage enables the controlling of a zener voltage. When ESD stress is present at the integrated circuit pad the diode, of either type, goes into a controllable voltage level breakdown.

A new method of forming a thick oxide MOS transistor for electrostatic discharge protection in a standard sub-micron STI CMOS process for an integrated circuit device has been achieved. A first well and a second well are implanted. The wells are counter-doped to the substrate type. The first well forms the drain, and the second well forms the source. A thin oxide layer is formed. A polysilicon layer is deposited. The polysilicon layer is patterned to form a dummy floating gate. Ions are implanted into the first well to form a first lightly-doped region and into the second well to form a second lightly-doped region of the same type as the wells. The lightly-doped regions are self-aligned to the dummy floating gate. Sidewall spacers are formed on the floating dummy gates. Ions are implanted into the first well to form a first heavily-doped region and the second well to to form a second heavily-doped region of the same type as the wells. The heavily-doped regions are self-aligned to the sidewall spacers. An interlevel dielectric layer is deposited. A metal layer is deposited overlying the interlevel dielectric layer. The metal layer is patterned to form the gate electrode.

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Singapore, Singapore

Cai Jun