Asan, South Korea

Byong-Joo Kim

This inventor holds 4 USPTO granted patents and 1 published patent application. Top assignee: Samsung Electronics Co., Ltd.. Active years: 2016-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Byong-Joo Kim. Retrieved from https://idiyas.com/inventor/byong-joo-kim

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 4 

% Patents Active = 75.0

Average Co-Inventor Count = 5.5

ph-index = 2

Forward Citations = 6(Granted Patents)


Company Filing History:


Years Active: 2016-2020

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4 patents (USPTO):Explore Patents

Title: Byong-Joo Kim: Semiconductor Packaging Inventor

Introduction

Byong-Joo Kim is an inventor based in Asan, South Korea. His work includes semiconductor packaging, and he is associated with Samsung Electronics Co., Ltd. Kim is credited with 4 patents.

Latest Patents

Kim’s listed recent patents focus on multi-chip packages and methods for manufacturing them. The inventions describe semiconductor chips stacked on a package substrate, with bonding pads, stud bumps, and conductive wires connecting the chips and substrate.

In the described arrangement, a wire from the lowermost chip connects to a substrate pad, while another wire extends upward and connects sequentially to stud bumps on the chips above it. These structures provide an approach to electrical connections within a stacked multi-chip package.

Career Highlights

Kim’s patent work reflects an emphasis on semiconductor assembly and interconnection. His listed inventions address the design and manufacture of multi-chip packages, technologies used to integrate multiple semiconductor chips into a single package.

Collaborations

Kim’s listed coworkers include Won-Gil Han and Yong-Je Lee. The patent descriptions identify technical work involving stacked chips, package substrates, stud bumps, and conductive wires.

Conclusion

Byong-Joo Kim’s patent portfolio highlights contributions to multi-chip semiconductor packaging, particularly methods for connecting stacked chips within a package.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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