Samsung Electronics Co., Ltd.

Byong-Joo Kim

Won-Gil Han

Yong-Je Lee

Seung-Weon Ha

Jae-Heung Lee

Min Seop Kim

Ho-Tae Jin

Yean-Sang You

Do-Hoon Lee

Se-Yeoul Park

Han-Ki Park

Ho-Am Kim

A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

Method of manufacturing multi-chip package

Multi-chip package and method of manufacturing the same

In a method of detecting faults of operation algorithms in a wire bonding machine, individual bond parameters with respect to each of the operation algorithms of the wire bonding machine can be set based on design data including information with respect to conductive wires connected between semiconductor chips of a semiconductor package. Actual conductive wires of an actual semiconductor package can be formed using the wire bonding machine into which the design data can be inputted. Actual data with respect to actual operation algorithms of the wire bonding machine, which can form the actual conductive wires, can be obtained. The actual data can be compared with the individual bond parameters to detect the faults of the operation algorithms of the wire bonding machine. Thus, forming an abnormal conductive wire by the wire bonding machine can be prevented beforehand.

Method of detecting faults of operation algorithms in a wire bonding machine and apparatus for performing the same

A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.

Growing community of inventors

Asan-si, South Korea

Byong-Joo Kim