The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 2016
Filed:
Oct. 03, 2014
Samsung Electronics Co., Ltd., Suwon-si, KR;
Won-Gil Han, Asan-si, KR;
Se-Yeoul Park, Cheonan-si, KR;
Ho-Tae Jin, Cheonan-si, KR;
Byong-Joo Kim, Asan-si, KR;
Yong-Je Lee, Asan-si, KR;
Han-Ki Park, Cheonan-si, KR;
SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, KR;
Abstract
A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.