Brian J Kaczynski

Title: Brian J Kaczynski: Innovator in Asynchronous Digital Circuits

Introduction

Brian J Kaczynski is a notable inventor based in Los Altos, CA (US). He has made significant contributions to the field of digital circuit design, holding a total of 7 patents. His work focuses on enhancing the efficiency and performance of asynchronous digital circuits.

Latest Patents

One of Kaczynski's latest patents is titled "Controlling timing in asynchronous digital circuits." This invention provides a timing circuit for generating asynchronous signals that utilizes minimal area while maximizing speed. The circuit includes a timing control block and disable/enable circuitry, featuring an SR latch that generates first and second asynchronous signals. The design incorporates first and second delay blocks that generate delayed signals, ensuring that positive and negative edges of the signals are treated differently.

Another significant patent is "Stacking baseband circuits using deep n-well and increased supply voltage." This method describes the design of stacked circuits for integrated circuits, where a subset of stackable devices is formed in a deep n-well to receive an increased supply voltage. This innovative approach allows for improved performance in the design and implementation of stacked circuits.

Career Highlights

Brian J Kaczynski is currently employed at Atheros Communications, Inc., where he continues to develop cutting-edge technologies in digital circuit design. His expertise in asynchronous circuits has positioned him as a key player in the industry.

Collaborations

Kaczynski has collaborated with Srenik Suresh Mehta, working together to advance their research and development efforts in the field of digital circuits.

Conclusion

Brian J Kaczynski's contributions to asynchronous digital circuits demonstrate his innovative spirit and technical expertise. His patents reflect a commitment to enhancing circuit design, making a lasting impact in the field.