Atheros Communications, Inc.

Brian J Kaczynski

Srenik Suresh Mehta

A timing circuit for generating asynchronous signals is provided that uses minimal area while maximizing speed. This timing circuit can include a timing control block and disable/enable circuitry. The timing control block can include an SR latch and first and second delay blocks. The SR latch can generate first and second signals, wherein the first and second signals are asynchronous. The first delay block can generate a delayed first signal and provide that signal to a first input terminal of the SR latch. Similarly, the second delay block can generate a delayed second signal and provide that signal to a second input terminal of the SR latch. Notably, the first and second delay blocks delay positive going edges of the first and second signals differently than negative going edges of the first and second signals.

Controlling timing in asynchronous digital circuits

A method of designing stacked circuits for an integrated circuit is described. In this method, a plurality of devices that are stackable may be determined. Some of those devices, i.e. a subset of stackable devices, may be formed in a deep n-well, thereby allowing that subset of stackable devices to receive an increased supply voltage. The remainder of the stackable devices may be formed in a standard n-well, thereby allowing such devices to receive a standard supply voltage. In one embodiment, the standard supply voltage may be VDD and the increased supply voltage may be 2&#xd7;VDD. This method may be advantageously used in both the design of stacked circuits for and the implementation of stacked circuits in an integrated circuit.

Stacking baseband circuits using deep n-well and increased supply voltage

An RF coupling circuit including a transformer and a parallel AC-coupling capacitor can advantageously ameliorate substantial attenuation of a signal, prevent destabilization of any feedback loop, and simplify the circuit design process. The AC-coupling capacitor can act as an 'averager', i.e. both the input and output sides of coupling circuit represent capacitances equal to the average of the input and the output capacitances. Thus, the inductors for tuning them out can become equal, thereby allowing a symmetric (or near symmetric) transformer to be used in the RF coupling circuit. When tuned properly, the transformer plus AC-coupling capacitor can also advantageously provide better in-band gain as well as frequency selectivity than other conventional coupling circuits.

Inter-stage coupling with a transformer and parallel AC-coupling capacitor

A transceiver includes a power control circuit in the transmitter that operates on a packet-by-packet basis. The transceiver can, for each packet, set a variable gain amplifier to a first gain and use predetermined gain increments to thereafter increase gain until a gain hold event. The gain hold event can be an expiration of a time duration allocated for changing gain or a desired power being reached, whichever event occurs first. The gain can be adjusted by a predetermined amount based on an operating condition.

Power control on a packet-by-packet basis in a CMOS transceiver

The present invention includes a transceiver and a method of operating the same that includes in the transmitter a power control circuit that operates on an analog differential signal containing data packets individually. The power control circuit initially transmits a series of data symbols with known values, periodically strobes the transceiver system for correct power levels and incrementally increases the power level of the transceiver until the optimal gain is reached, without exceeding the maximum output power.

Method and apparatus for a transceiver having a constant power output

A channel select filter circuit is disclosed using a current-mode transconductance-capacitor (gm-C) architecture, which is tuned by digitally controlled capacitor arrays. The main filter includes at least one transconductor-capacitor (gm-C) filter and a transresistance amplifier. A replica transconductor-capacitor (gm-C) filter and a phase detector are used to establish any phase shift in an input signal, and a state machine adjusts capacitor arrays in the the replica transconductor-capacitor (gm-C) filter and the at least one transconductor-capacitor (gm-C) filter in order to set a cut-off frequency of the channel select filter.

Growing community of inventors

Los Altos, CA, United States of America

Brian J Kaczynski