The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 12, 2010
Filed:
Mar. 20, 2007
Brian J. Kaczynski, Santa Clara, CA (US);
Brian J. Kaczynski, Santa Clara, CA (US);
Atheros Communications, Inc., San Jose, CA (US);
Abstract
A method of designing stacked circuits for an integrated circuit is described. In this method, a plurality of devices that are stackable may be determined. Some of those devices, i.e. a subset of stackable devices, may be formed in a deep n-well, thereby allowing that subset of stackable devices to receive an increased supply voltage. The remainder of the stackable devices may be formed in a standard n-well, thereby allowing such devices to receive a standard supply voltage. In one embodiment, the standard supply voltage may be VDD and the increased supply voltage may be 2×VDD. This method may be advantageously used in both the design of stacked circuits for and the implementation of stacked circuits in an integrated circuit.