Austin, TX, United States of America

Brett Stanley Feero

This inventor holds 25 USPTO granted patents and 2 published patent applications and 3 EPO patents, primarily in Computer Architecture. Top assignees: Apple Inc., Arm Limited. Active years: 2012-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Brett Stanley Feero. Retrieved from https://idiyas.com/inventor/brett-stanley-feero

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 25 

% Patents Active = 100.0

 

Average Co-Inventor Count = 2.8

ph-index = 5

Forward Citations = 61(Granted Patents)


Location History:

  • Cambridge, GB (2012)
  • Justin, TX (US) (2021)
  • Austin, TX (US) (2013 - 2023)
  • Lake Oswego, OR (US) (2023 - 2024)

Company Filing History:


Years Active: 2012-2025

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Areas of Expertise:
Cache Invalidation
Coprocessor Operations
Parallel Execution
Real-Time Processing
Memory Ordering
Pipeline Optimization
Branch Predictor
Data Transfer
Clock Synchronization
Shared Cache Control
Transaction Requests
Integrated Circuit
25 patents (USPTO):Explore Patents

Title: Brett Stanley Feero: Innovator in Processor Technology

Introduction

Brett Stanley Feero, based in Austin, TX, is a prominent inventor recognized for his significant contributions to processor technology. With an impressive portfolio of 24 patents, he stands out as an influential figure in the field of computing and processor design.

Latest Patents

Two of Brett's latest patents showcase his innovative approach to processing technologies. The first patent, titled "Coprocessor Operation Bundling," describes a processor design that includes a buffer within an interface unit. This buffer accumulates coprocessor instructions before they are transmitted, optimizing the delivery process to ensure the coprocessor's instruction consumption matches the average rate of instruction provision.

The second patent, "Processor Implementing Parallel In-Order Execution During Load Misses," introduces a method whereby an instruction pipeline continues to execute subsequent instructions even when data for an initial instruction is missing. This design enhances efficiency by reducing stalls during data loading and allows the processor to maintain a steady execution flow until a specific condition necessitates halting.

Career Highlights

Brett Stanley Feero has made a notable impact in his career by working at prestigious companies such as Apple Inc. and Arm Limited. His work in these leading organizations has contributed to advancements in technology and processor design, marking him as a key player in the tech industry.

Collaborations

Throughout his career, Brett has collaborated with talented individuals, including Nikhil Gupta and Michael Filippo. These partnerships have facilitated the exchange of ideas and fostered innovation in the projects they have undertaken together.

Conclusion

Brett Stanley Feero's extensive patent portfolio and groundbreaking patents reflect his dedication to enhancing processor technology. His contributions not only advance technical capabilities but also pave the way for future innovations in the computing industry. With his continued work and collaboration with other brilliant minds, the future of processor technology looks promising.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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