Apple Inc.

Arm Limited

Brett Stanley Feero

Aditya Kesiraju

Nikhil Gupta

Michael Filippo

David James Williamson

David Edward Kroesche

Jamshed Jalal

Mark David Werkheiser

Viney Gautam

Ian D Kountanis

Conrado Blasco

Shih-Chieh Wen

Andrew David Tune

Ronald P Hall

Phanindra Kumar Mannava

Mary Douglass Brown

Klas Magnus Bruce

Bernard Joseph Semeria

Rohit Kumar Gupta

Richard F Russo

Gaurav Garg

James Vash

Michael Andrew Campbell

Peter Andrew Riocreux

Michael Lance Karm

Ramamoorthy Guru Prasadh

Jeff Gonion

Jonathan Jay Tyler

Deepak Limaye

Timothy Nicholas Hay

Jonathan Y Tong

Christopher Colletti

Christopher Edwin Wrigley

Michael D Snyder

Matthew C Stone

Justin M Deinlein

So Min Song

Gagan Anand

Jonathan Ying Fai Tong

Sendil Srinivasan

Techniques are disclosed relating to performing remote cache invalidations. In some embodiments, primary processor circuitry is configured to, based on execution of a remote invalidate instruction (e.g., an ISA-defined instruction), send a cache invalidate command to coprocessor circuitry. The coprocessor circuitry includes coprocessor cache circuitry and cache invalidation control circuitry configured to, in response to the cache invalidate command sent by the primary processor, invalidate one or more cache lines in the coprocessor cache circuitry without executing any instructions on the coprocessor circuitry.

Remote cache invalidation

In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

Coprocessor operation bundling

A processor may include an instruction pipeline that executes program instructions in-order according to a program order. During operation, the instruction pipeline may detect that data is missing for a first instruction. In response, the instruction pipeline may send a request to load the missing data for the first instruction. However, the instruction pipeline may not necessarily stall operation to wait for the missing data to be loaded. Instead, the instruction pipeline may continue executing instructions subsequent to the first instruction. During the continued execution, the instruction pipeline may detect that data is missing for a second instruction, and send a request to load the missing data for the second instruction. The instruction pipeline may continue such operation until it determines that a condition occurs that prevents the continued execution. When the condition occurs, the instruction pipeline may stop the continued execution, and then re-execute the first instruction.

Processor implementing parallel in-order execution during load misses

An embodiment of an apparatus includes a processing circuit and a system memory. The processing circuit may store a pending request in a buffer, the pending request corresponding to a transaction that includes a write request to the system memory. The processing circuit may also allocate an entry in a write table corresponding the transaction. After sending the transaction to the system memory to be processed, the pending request in the buffer may be removed in response to the allocation of the write entry.

Virtual channel support using write table

A processor configured for real-time transaction processing is disclosed. A processor circuit includes configuration registers that designate a first range of physical memory addresses as reserved for real-time memory requests and a second, non-overlapping range of physical memory addresses that are shared between real-time and non-real-time memory requests. In response to determining that a memory request is associated with an address in the first range, the processor tags the request as a real-time request. The configuration registers may also store information designating portions of one or more cache memories and one or more buffers as being reserved for real-time memory requests. During arbitration, real-time memory requests are given priority over older, non-real-time memory requests.

Real-time processing in computer systems

A processor with reduced interrupt latency is disclosed. An apparatus includes a processor core and a cache subsystem having a cache controller and a cache. The processor core is configured to submit, to the cache controller, requests for access to the cache, wherein a given request for access to the cache specifies whether the given request is abandonable or non-abandonable in an event of an interrupt request. In response to a particular interrupt request, the processor core may provide an indication to cause the cache controller to abandon requests for access to the cache identified as abandonable. After receiving an acknowledgement from the cache controller that the abandonable requests have been abandoned, the processor core may begin execution of an interrupt handler in order to service the interrupt request.

Processor with reduced interrupt latency

In an embodiment, an apparatus includes a plurality of memories configured to store respective data in a plurality of branch prediction entries. Each branch prediction entry corresponds to at least one of a plurality of branch instructions. The apparatus also includes a control circuit configured to store first data associated with a first branch instruction into a corresponding branch prediction entry in at least one memory of the plurality of memories. The control circuit is further configured to select a first memory of the plurality of memories, to disconnect the first memory from a power supply in response to a detection of a first power mode signal, and to cease storing data in the plurality of memories in response to the detection of the first power mode signal.

Methods for partially preserving a branch predictor state

In an embodiment, at least one CPU processor and at least one coprocessor are included in a system. The CPU processor may issue operations to the coprocessor to perform, including load/store operations. The CPU processor may generate the addresses that are accessed by the coprocessor load/store operations, as well as executing its own CPU load/store operations. The CPU processor may include a memory ordering table configured to track at least one memory region within which there are outstanding coprocessor load/store memory operations that have not yet completed. The CPU processor may delay CPU load/store operations until the outstanding coprocessor load/store operations are complete. In this fashion, the proper ordering of CPU load/store operations and coprocessor load/store operations may be maintained.

Coprocessor memory ordering table

An apparatus includes a control circuit and a cache memory with a plurality of regions. The control circuit receives a first and a second access request to access the cache memory. In response to determining that the first access request is from a particular processor core, and that the first access request is associated with a particular cache line in the cache memory, the control circuit stores the first access request in a cache access queue. In response to a determination that the second access request is received from a functional circuit, and that the second access request is associated with a range of a memory address space mapped to a subset of the plurality of regions, the control circuit stores the second access request in a memory access queue. The control circuit arbitrates access to the cache memory circuit between the first access request and the second access request.

Using cache memory as RAM with external access support

In various embodiments, a branch prediction redirection system may include a first branch prediction circuit configured to predict a first target of a branch instruction and a second branch prediction circuit configured to predict a second target of the branch instruction. A redirection circuit may send a pipeline redirection indication in response to the first target differing from the second target. A suppression circuit may prevent the pipeline redirection indication from being sent in response to identifying that data corresponding to the branch instruction indicates a potential multi-hit.

Suppressing pipeline redirection indications

In an embodiment, an apparatus includes a first buffer, a second buffer, and a control circuit. The control circuit may be configured to receive a first plurality of instructions included in a program. The control circuit may also be configured to store each of the first plurality of instructions in an entry of a first number of entries in the first buffer, arranged in the first number of entries dependent upon a received order. The control circuit may be further configured to select a second plurality of instructions from the first buffer. The second plurality of instructions may be selected dependent upon a program order. The control circuit may be configured to store each of the second plurality of instructions in an entry of a second number of entries in the second buffer, arranged in the second number of entries dependent upon the program order.

Ordering instructions in a processing core instruction buffer

Methods for partially saving a branch predictor state

Growing community of inventors

Austin, TX, United States of America

Brett Stanley Feero