New Taipei, Taiwan

Bo Wei Wu

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Bo Wei Wu. Retrieved from https://idiyas.com/inventor/bo-wei-wu-zfiaa7hw

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Bo Wei Wu and Semiconductor Memory Architecture.

Introduction

Bo Wei Wu is an inventor based in New Taipei, Taiwan. His patent work includes semiconductor structures designed to support memory signal transmission through front-side and backside interconnects.

Latest Patents

Wu is associated with 1 patent: “Semiconductor Structure Including Memory Signal Transmission Line in Backside Redistribution.” The invention describes a semiconductor substrate with front and backside surfaces, a substrate layer, and two active layers. A data storage element extends across both active layers. The structure also includes two bit-line sets, with at least one line in the first set positioned on the front side and at least one line in the second set positioned on the backside.

Career Highlights

Wu is associated with Taiwan Semiconductor Manufacturing Company Limited. His patent reflects work on semiconductor memory structures and signal routing across different sides of a substrate.

Collaborations

The provided information identifies Ze-Xian Lu and PO-Hsun Chu as Wu’s coworkers. Their specific roles in the patent or related work are not stated.

Conclusion

Bo Wei Wu’s recorded patent focuses on integrating memory elements and bit-line connections across the front and backside of a semiconductor substrate.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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