San Jose, CA, United States of America

Bhuvnesh Kumar

This inventor holds 2 USPTO granted patents. Top assignee: Synopsys, Inc.. Active years: 2025-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Bhuvnesh Kumar. Retrieved from https://idiyas.com/inventor/bhuvnesh-kumar-sy07t8yf

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 50.0

Average Co-Inventor Count = 4.0

ph-index = 1


Company Filing History:


Years Active: 2025-2026

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2 patents (USPTO):Explore Patents

Title: Bhuvnesh Kumar: Innovator in Circuit Testing Technology

Introduction

Bhuvnesh Kumar is a notable inventor based in San Jose, California. He has made significant contributions to the field of circuit testing through his innovative methods. His work focuses on enhancing the reliability and efficiency of circuit designs.

Latest Patents

Bhuvnesh Kumar holds a patent for "Constrained random simulation using machine learning and Bayesian estimation." This patent outlines a method for circuit testing that includes determining a probability distribution indicating prior failure probabilities associated with a circuit design. It also involves assessing the likelihood of failures and calculating the necessary test instances to detect these failures effectively.

Career Highlights

Bhuvnesh Kumar is currently employed at Synopsys, Inc., a leading company in electronic design automation. His role involves applying advanced simulation techniques to improve circuit testing processes. His innovative approach has garnered attention in the industry.

Collaborations

Bhuvnesh has collaborated with talented individuals such as Ganapathy Parthasarathy and Saurav Nanda. These collaborations have contributed to the advancement of technology in circuit testing.

Conclusion

Bhuvnesh Kumar's work exemplifies the intersection of machine learning and circuit testing, showcasing his commitment to innovation in the field. His contributions are paving the way for more reliable electronic designs.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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