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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12399219 B1

PDFFull Text
Date of Patent:
Aug. 26, 2025

Filed:

Aug. 18, 2023

Constrained random simulation using machine learning and bayesian estimation

Applicant:

Synopsys, Inc., Sunnyvale, CA (US);

Inventors:

Bhuvnesh Kumar, San Jose, CA (US);

Ganapathy Parthasarathy, Fremont, CA (US);

Saurav Nanda, San Jose, CA (US);

Sridhar Rajakumar, Fremont, CA (US);

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:

Patterson + Sheridan, LLP

Primary Examiner:

Esaw T Abraham

Int. Cl.
CPC ...
G01R 31/317 (2006.01); G01R 31/3177 (2006.01); G01R 31/3183 (2006.01); G01R 31/3185 (2006.01); G06F 11/26 (2006.01); G06F 11/267 (2006.01); G06F 11/27 (2006.01); G06F 11/34 (2006.01); G06N 7/01 (2023.01);
U.S. Cl.
CPC ...
G01R 31/318357 (2013.01); G06N 7/01 (2023.01);
Abstract

Certain aspects of the present disclosure are directed towards a method for circuit testing. The method generally includes: determining a probability distribution indicating prior failure probabilities associated with a circuit design; determining a first likelihood associated with occurrence of at least one failure for the circuit design; determining a quantity of test instances to be performed using simulation to detect the at least one failure based on the probability distribution and the first likelihood; and outputting the quantity of test instances.

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