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Kawasaki, Japan

Atsuhiko Ikeuchi

This inventor holds 8 USPTO granted patents. Top assignee: Kabushiki Kaisha Toshiba. Active years: 2004-2011.

USPTO Granted Patents = 8

Average Co-Inventor Count = 1.6

ph-index = 6

Forward Citations = 303(Granted Patents)

Location History:

Kanagawa-ken, JP (2004 - 2006)
Kawasaki, JP (2004 - 2009)
Kanagawa, JP (2008 - 2011)

Company Filing History:

8 out of 53,250

Kabushiki Kaisha Toshiba

Years Active: 2004-2011

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8 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 7958463 - Computer automated method for manufacturing an integrated circuit pattern layout (2011-06-07),

2. 7559044 - Automatic design method of semiconductor integrated circuit, automatic design system of semiconductor integrated circuit, and semiconductor integrated circuit (2009-07-07),

3. 7451429 - Computer automated method for optimizing an integrated circuit pattern in a layout verification process (2008-11-11),

4. 7418694 - Method for generating test patterns utilized in manufacturing semiconductor device (2008-08-26),

5. 7124389 - Automated wiring pattern layout method (2006-10-17),

6. 6952818 - Method and system for optical proximity correction (2005-10-04),

7. 6792593 - Pattern correction method, apparatus, and program (2004-09-14),

8. 6779167 - Automated wiring pattern layout method (2004-08-17),

Profile summary based on public USPTO records.

Please report any incorrect information to [email protected]

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