Kabushiki Kaisha Toshiba

Atsuhiko Ikeuchi

Koji Hashimoto

Masaaki Yamada

Mutsunori Igarashi

Makoto Takashima

Sachiko Kobayashi

A computer automated method for designing an integrated circuit includes placing a plurality of marks on each of contours of a plurality of patterns allocated in a chip area; dividing the marks into a plurality of groups so that the adjacent marks are merged in a same group; determining one of the groups as a candidate hot spot based on a total number of marks included in each of the groups; and modifying the corresponding pattern in the candidate hot spot.

Computer automated method for manufacturing an integrated circuit pattern layout

An automatic design method of a semiconductor integrated circuit includes: increasing an interval between a plurality of wiring patterns provided on a chip region to relieve a density of the wiring patterns based on first reference information including a criterion about a restriction of wiring length and second reference information including a criterion for a reduction of defect; verifying a circuit characteristic for the result of the relief; first thickening the wiring pattern by using a first design rule having a first correction value for thickening the wiring pattern; and second thickening the wiring pattern having been thickened in said first thickening by using a second design rule having a second correction value higher than the first correction value.

Automatic design method of semiconductor integrated circuit, automatic design system of semiconductor integrated circuit, and semiconductor integrated circuit

Computer automated method for optimizing an integrated circuit pattern in a layout verification process

A method for generating test patterns utilized in manufacturing a semiconductor device includes creating mini-data concerning a partial area pattern used in designing the semiconductor device, subjecting the mini-data to data processing in accordance with a condition of a manufacturing process of the semiconductor device, thereby creating processed mini-data, extracting a marginless point in the processed mini-data where a process margin is less than a predetermined threshold in a manufacturing process of the semiconductor device, determining a class of the marginless point in accordance with a criticality and a category of the marginless point, determining a parameter and a range of the parameter used for the marginless point in accordance with the class of the marginless point, and generating a plurality of test patterns to which different values of the parameter are respectively applied within the range.

Method for generating test patterns utilized in manufacturing semiconductor device

An automated wiring pattern layout method is provided. With this method, a first wiring pattern is generated with width W and extending in a first direction, and a second wiring pattern is generated with width W and extending in a direction perpendicular to the first wiring pattern in a manner such that the end thereof ends at the end portion of the first wiring pattern. Moreover, an overlapping region is generated by bending an end of either one of the first or the second wiring pattern at a right angle to produce an L-shaped extension and overlaying the first and the second wiring pattern, and a rectangular-shaped VIA pattern is generated at the overlapping region.

Automated wiring pattern layout method

A computer implemented method for OPC includes: storing an improper OPC pattern and a corrective treatment for the improper OPC pattern in a library storage medium; reading a layout pattern; and matching the layout pattern with the improper OPC pattern stored in the library storage medium.

Method and system for optical proximity correction

In a pattern correction method, design layout data of a pattern designed by an automated layout unit is entered. An environmental profile is determined based on whether or not another graphics pattern exists at the surroundings of each correction target cell included in the entered design layout data. A target cell name is replaced with a prescribed cell name of correction pattern corresponding to the determined environmental profile by referencing a cell replacement table. An OPC correction pattern corresponding to the replaced cell name is imported from a cell library.

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Kawasaki, Japan

Atsuhiko Ikeuchi