Saratoga, CA, United States of America

Arindam Chatterjee

This inventor holds 3 USPTO granted patents and 1 published patent application. Top assignee: Synopsys, Inc.. Active years: 2017-2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Arindam Chatterjee. Retrieved from https://idiyas.com/inventor/arindam-chatterjee-afdjofbv

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 3 

% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1


Company Filing History:


Years Active: 2017-2019

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3 patents (USPTO):Explore Patents

Title: Arindam Chatterjee: Innovator in Capacitance Reduction Technologies

Introduction

Arindam Chatterjee is a notable inventor based in Saratoga, CA (US). He has made significant contributions to the field of capacitance reduction technologies, holding a total of 3 patents. His work focuses on innovative methods that enhance the efficiency of interconnect structures in electronic devices.

Latest Patents

One of his latest patents is titled "Floating node reduction using random walk method." This method utilizes a capacitance matrix that specifies coupling capacitances between signal nodes and floating nodes of an interconnect structure. Random walks are performed from a first signal node to other signal nodes, with each walk directed based on probabilities derived from the coupling capacitances. This innovative approach maintains a count for each signal node, allowing for precise calculations of indirect coupling capacitance.

Another significant patent is "Parasitic-aware blockage." This invention provides a parasitic-aware blockage structure that replaces detailed blockage structures used in capacitance extraction operations. The structure includes one or more parasitic-aware blockage polygons, which represent multiple polygons of the detailed blockage structure. This advancement allows for better physical information association and capacitive error specification, enhancing the accuracy of capacitance extraction.

Career Highlights

Arindam Chatterjee is currently employed at Synopsys, Inc., a leading company in electronic design automation. His work at Synopsys has allowed him to further develop his innovative ideas and contribute to cutting-edge technologies in the industry.

Collaborations

Throughout his career, Arindam has collaborated with notable coworkers, including Alexei Svizhenko and Arthur Nieuwoudt. These collaborations have fostered a creative environment that encourages the development of groundbreaking technologies.

Conclusion

Arindam Chatterjee's contributions to capacitance reduction technologies demonstrate his innovative spirit and dedication to advancing the field. His patents reflect a deep understanding of electronic design and a commitment to improving interconnect structures.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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