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Acton, MA, United States of America

Anthony Jarvis

USPTO Granted Patents = 21 


Average Co-Inventor Count = 2.1

ph-index = 4

Forward Citations = 78(Granted Patents)


Location History:

  • Acton, MA (US) (2004 - 2017)
  • Boston, MA (US) (2020)
  • Boxborough, MA (US) (2020 - 2022)

Company Filing History:

goldMedal13 out of 12,867 
 
Advanced Micro Devices Corporation
 patents
silverMedal8 out of 2,867 
 
Stmicroelectronics Gmbh
 patents
bronzeMedal2 out of 9,638 
 
Hewlett-packard Company
 patents
4. 1 out of 27,394 
 
Hewlett-packard Development Company, L.p.
 patents
where one patent can have more than one assignee

Years Active: 2004-2025

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21 patents (USPTO):
1. 12282776 - Hybrid parallelized tagged geometric (TAGE) branch prediction (2025-04-21),
2. 12153927 - Merged branch target buffer entries (2024-11-26),
3. 11416253 - Multiple-table branch target buffer (2022-08-16),
4. 11256505 - Using loop exit prediction to accelerate or suppress loop mode of a processor (2022-02-22),
5. 11216279 - Loop exit predictor (2022-01-04),
6. 10915322 - Using loop exit prediction to accelerate or suppress loop mode of a processor (2021-02-09),
7. 10713054 - Multiple-table branch target buffer (2020-07-14),
8. 10635591 - Systems and methods for selectively filtering, buffering, and processing cache coherency probes (2020-04-28),
9. 9778934 - Power efficient pattern history table fetch in branch predictor (2017-10-03),
10. 8788797 - Combined level 1 and level 2 branch predictor (2014-07-22),
11. 8667257 - Detecting branch direction and target address pattern and supplying fetch address by replay unit instead of branch prediction unit (2014-03-04),
12. 8578141 - Loop predictor and method for instruction fetching using a loop predictor (2013-11-05),
13. 8181005 - Hybrid branch prediction device with sparse and dense prediction caches (2012-05-15),
14. 7757066 - System and method for executing variable latency load operations in a date processor (2010-07-13),
15. 7143268 - Circuit and method for instruction compression and dispersal in wide-issue processors (2006-11-28),

As an AI assistant specializing in innovations, inventions, inventors, patent attorneys, assignees, and patents, I recommend discussing inventor Anthony Jarvis and his notable contributions in the field of processor technologies. Here is an article based on the provided data:

Title: Innovator Spotlight: Anthony Jarvis, Shaping Future Processor Technologies

Introduction:

Anthony Jarvis, a prolific inventor hailing from Acton, MA (US), has made significant strides in the realm of processor designs and optimization. With 19 patents to his name, Jarvis is admired for his innovative solutions that enhance instruction processing speed and efficiency.

Latest Patents:

Among his latest patents is the 'Multiple-table Branch Target Buffer', which revolutionizes branch prediction in processors. By employing multiple BTB tables with varying target sizes and types, this invention optimizes instruction processing speed and resource utilization. Additionally, the 'Loop Exit Prediction' patent showcases Jarvis's expertise in accelerating processor performance through efficient loop execution strategies.

Career Highlights:

Jarvis has honed his expertise through collaborations with esteemed companies in the industry. Notably, he has contributed his technical acumen to Advanced Micro Devices Corporation and STMicroelectronics GmbH, where his innovative spirit flourished, leading to groundbreaking advancements in processor technologies.

Collaborations:

During his career, Jarvis has had the privilege of working alongside accomplished colleagues such as Mark Owen Homewood and Paolo Faraboschi. These collaborations have not only enriched his professional journey but have also paved the way for pioneering developments in the field of processor architecture.

Conclusion:

In conclusion, Anthony Jarvis stands as a beacon of innovation in the realm of processor technologies. His inventive solutions have redefined branch prediction mechanisms and loop execution strategies, setting new standards for efficiency and performance in modern processors. With a rich portfolio of patents and a legacy of impactful collaborations, Jarvis continues to inspire and drive advancements in the ever-evolving landscape of computational technologies.

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