The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2006
Filed:
Dec. 29, 2000
Paolo Faraboschi, Brighton, MA (US);
Anthony X. Jarvis, Acton, MA (US);
Mark Owen Homewood, Winscombe, GB;
Geoffrey M. Brown, Watertown, MA (US);
Gary L. Vondran, San Carlos, CA (US);
Paolo Faraboschi, Brighton, MA (US);
Anthony X. Jarvis, Acton, MA (US);
Mark Owen Homewood, Winscombe, GB;
Geoffrey M. Brown, Watertown, MA (US);
Gary L. Vondran, San Carlos, CA (US);
STMicroelectronics, Inc., Carrollton, TX (US);
Hewlett-Packard Development Co., L.P., Houston, TX (US);
Abstract
A data processor includes execution clusters, an instruction cache, an instruction issue unit, and alignment and dispersal circuitry. Each execution cluster includes an instruction execution pipeline having a number of processing stages, and each execution pipeline is a number of lanes wide. The processing stages execute instruction bundles, where each instruction bundle has one or more syllables. Each lane is capable of receiving one of the syllables of an instruction bundle. The instruction cache includes a number of cache lines. The instruction issue unit receives fetched cache lines and issues complete instruction bundles toward the execution clusters. The alignment and dispersal circuitry receives the complete instruction bundles from the instruction issue unit and routes each received complete instruction bundle to a correct one of the execution clusters. The complete instruction bundles are routed as a function of at least one address bit associated with each complete instruction bundle.