Bengaluru, India

Anmol Khatri

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Intel Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Anmol Khatri. Retrieved from https://idiyas.com/inventor/anmol-khatri

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 6.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Anmol Khatri: Innovating Machine-Learning-Based Circuit Timing Predictions.

Introduction

Anmol Khatri is an inventor based in Bengaluru, India, whose patent work addresses the use of machine learning to predict input/output timing constraints for system-on-chip designs. The disclosed approach combines design-delay features with model-based estimates to help assess and update circuit timing information.

Latest Patents

Khatri is associated with 1 patent, titled “Methods and Apparatus to Generate Circuit Timing Constraint Predictions Using Machine Learning.” The patent describes extracting delay features from two system-on-chip designs and applying a machine-learning model to estimate delay for one design. The estimated delay is compared with the other design to determine an error, which is then used to update the second design. The disclosed apparatus may include memory, machine-readable instructions, and processor circuitry.

Career Highlights

Khatri works at Intel Corporation. His patent reflects work at the intersection of machine learning and semiconductor design, with a focus on generating and refining timing constraints for system-on-chip development.

Collaborations

The provided information identifies Lekshmi C and Sourav Saha as Khatri’s coworkers. Their specific roles in the patent or related work are not stated.

Conclusion

Anmol Khatri’s patent describes a machine-learning-based method for estimating circuit delays and using prediction errors to improve timing information for system-on-chip designs.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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