Methods and apparatus to generate circuit timing constraint predictions using machine learning

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed for methods and apparatus to generate I/O timing constraint predictions for system-on-chips using machine learning. An apparatus is disclosed herein comprising at least one memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to extract delay features from a first system-on-chip design and a second system-on-chip design, apply a machine learning model to the extracted delay features to determine an estimated delay for the first system-on-chip design, compare the estimated delay for the first system-on-chip design to the second system-on-chip design to determine an error of the first system-on-chip design, and update the second system-on-chip design based on the error determined for the first system-on-chip design.