Berkeley, CA, United States of America

Andrew Waterman

This inventor holds 18 USPTO granted patents and 12 published patent applications and 5 EPO patents, primarily in Processor Architecture. Top assignee: Sifive, Inc.. Active years: 2021-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Andrew Waterman. Retrieved from https://idiyas.com/inventor/andrew-waterman

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 18 

% Patents Active = 100.0

 

Average Co-Inventor Count = 2.1

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:


Years Active: 2021-2026

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Areas of Expertise:
Power Management
Instruction Throttling
Vector Register File
Atomic Memory Operations
Macro-op Fusion
Memory Protection
Pipeline Architecture
Speculative Execution
Fetch Stage Handling
Vector Operations
Memory Access Faults
Address Translation
18 patents (USPTO):Explore Patents

Title: The Innovations of Andrew Waterman

Introduction

Andrew Waterman is a prominent inventor based in Berkeley, California. He has made significant contributions to the field of technology, particularly in the area of memory processing and instruction execution. With a total of 13 patents to his name, Waterman's work has had a substantial impact on the development of efficient computing systems.

Latest Patents

Among his latest patents is the invention titled "Efficient processing of masked memory accesses." This patent discloses systems and methods for processing masked memory accesses, including handling fault exceptions and checking memory attributes of memory regions to be accessed. The implementation of this invention performs a two-level memory protection violation scheme for masked vector memory instructions. The first level memory check ignores mask information associated with a masked vector memory instruction and operates on a memory footprint associated with the instruction. If a memory protection violation is detected, a second level memory check evaluates mask information at a vector element level to determine whether a fault exception should be raised.

Another notable patent is "Fusion with destructive instructions." This invention describes systems and methods for fusing instructions in integrated circuits, such as processors. The fusion circuitry detects a sequence of macro-ops stored in a processor pipeline, determining a micro-op that is equivalent to the sequence for execution. This innovation enhances the efficiency of instruction processing in modern computing systems.

Career Highlights

Andrew Waterman is currently employed at SiFive, Inc., where he continues to innovate and develop cutting-edge technologies. His work at SiFive has positioned him as a key player in the advancement of RISC-V architecture and open-source hardware design.

Collaborations

Throughout his career, Waterman has collaborated with notable colleagues, including Krste Asanovic and Joshua R Smith. These partnerships have fostered a collaborative environment that encourages innovation and the sharing of ideas.

Conclusion

Andrew Waterman's contributions to technology through his patents and work at SiFive, Inc. highlight his role as a leading inventor in the field. His innovative approaches to memory processing and instruction execution continue to shape the future of computing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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