The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Apr. 11, 2022
Applicant:

Sifive, Inc., San Mateo, CA (US);

Inventors:

Joshua Smith, San Francisco, CA (US);

Krste Asanovic, Berkeley, CA (US);

Andrew Waterman, Berkeley, CA (US);

Assignee:

SiFive, Inc., San Mateo, CA (US);

Attorney:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 9/32 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3806 (2013.01); G06F 9/30054 (2013.01); G06F 9/322 (2013.01); G06F 9/3844 (2013.01); G06F 9/3867 (2013.01);
Abstract

Systems and methods are disclosed for fetch stage handling of indirect jumps in a processor pipeline. For example, a method includes detecting a sequence of instructions fetched by a processor core, wherein the sequence of instructions includes a first instruction, with a result that depends on an immediate field of the first instruction and a program counter value, followed by a second instruction that is an indirect jump instruction; responsive to detection of the sequence of instructions, preventing an indirect jump target predictor circuit from generating a target address prediction for the second instruction; and, responsive to detection of the sequence of instructions, determining a target address for the second instruction before the first instruction is issued to an execution stage of a pipeline of the processor core.


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