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For the Inventor, By the Inventor

Del Mar, CA, United States of America

Andrew B Kahng

This inventor holds 36 USPTO granted patents, primarily in Integrated Circuit Design. Top assignees: Tela Innovations, Inc., University of California, University of Michigan. Active years: 2000-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Andrew B Kahng. Retrieved from https://idiyas.com/inventor/andrew-b-kahng

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 36

% Patents Active = 22.2

Average Co-Inventor Count = 2.5

ph-index = 14

Forward Citations = 1,044(Granted Patents)


Location History:

  • Los Angeles, CA (US) (2000)
  • La Jolla, CA (US) (2015)
  • Delmar, CA (US) (2006 - 2020)

Company Filing History:

goldMedal20 out of 219 
 
Tela Innovations, Inc.
 patents
silverMedal15 out of 16,008 
 
University of California
 patents
bronzeMedal3 out of 3,525 
 
University of Michigan
 patents
4. 1 out of 1 
 
Blaze Dfm, Inc.
 patent
5. 1 out of 132,108 
 
Samsung Electronics Co., Ltd.
 patents
where one patent can have more than one assignee

Years Active: 2000-2026

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Areas of Expertise:
Integrated Circuit
Global Routing
Circuit Optimization
Gate-Length Biasing
Layout Adjustment
Dielectric Reliability
Transistor Design
Patterning Lithography
Static Timing Analysis
Wafer Topography
Mask Design
Fill Annotation
36 patents (USPTO):Explore Patents
1. 12572729 - Integrated-circuit global routing method (2026-03-10),
2. 10713406 - Multi-die IC layout methods with awareness of mix and match die integration (2020-07-14),
3. 9922161 - IC layout adjustment method and tool for improving dielectric reliability at interconnects (2018-03-20),
4. 9229686 - Accuracy configurable adders and methods (2016-01-05),
5. 9202003 - Gate-length biasing for digital circuit optimization (2015-12-01),
6. 9166567 - Data-retained power-gating circuit and devices including the same (2015-10-20),
7. 9069926 - Standard cells having transistors annotated for gate-length biasing (2015-06-30),
8. 8949768 - Standard cells having transistors annotated for gate-length biasing (2015-02-03),
9. 8869094 - Standard cells having transistors annotated for gate-length biasing (2014-10-21),
10. 8756555 - Standard cells having transistors annotated for gate-length biasing (2014-06-17),
11. 8751974 - Layout decomposition for double patterning lithography (2014-06-10),
12. 8635583 - Standard cells having transistors annotated for gate-length biasing (2014-01-21),
13. 8490043 - Standard cells having transistors annotated for gate-length biasing (2013-07-16),
14. 8402396 - Layout decomposition for double patterning lithography (2013-03-19),
15. 8185865 - Methods for gate-length biasing using annotation data (2012-05-22),

Title: The Innovative Journey of Andrew B Kahng

Introduction: Andrew B Kahng is a renowned inventor based in Del Mar, California. With a passion for technological advancements, he has made significant contributions to the field of innovation.

Latest Patents: Andrew B Kahng holds several patents in various technological domains, showcasing his diverse expertise and inventive spirit.

Career Highlights: Throughout his illustrious career, Andrew B Kahng has been at the forefront of groundbreaking inventions that have revolutionized the industry. His innovative solutions have paved the way for new possibilities in technology.

Collaborations: Andrew B Kahng has collaborated with leading experts and organizations in the field, fostering a culture of innovation and knowledge sharing. His collaborative efforts have led to the development of cutting-edge technologies.

Conclusion: Andrew B Kahng's dedication to innovation and his remarkable contributions to the field make him a true pioneer in the world of inventors. His inventive spirit continues to inspire future generations of innovators.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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