The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2015
Filed:
Apr. 04, 2014
Applicant:
Tela Innovations, Inc., Los Gatos, CA (US);
Inventors:
Puneet Gupta, Marina Del Ray, CA (US);
Andrew B. Kahng, Del Mar, CA (US);
Assignee:
Tela Innovations, Inc., Los Gatos, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G06F 17/5063 (2013.01); G06F 17/5068 (2013.01); G06F 2217/78 (2013.01);
Abstract
Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology that changes a nominal gate-length of a transistor to a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length.
Gupta, Puneet. (2015). Gate-length biasing for digital circuit optimization (U.S. Patent No. 9202003). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9202003
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile