The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2020
Filed:
Nov. 29, 2016
Applicant:
The Regents of the University of California, Oakland, CA (US);
Inventors:
Assignee:
The Regents of the University of California, Oakland, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/39 (2020.01); G06F 30/327 (2020.01); G06F 30/3312 (2020.01); G06F 30/337 (2020.01); G06F 30/398 (2020.01); G06F 30/396 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/327 (2020.01); G06F 30/337 (2020.01); G06F 30/3312 (2020.01); G06F 30/39 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 30/396 (2020.01); G06F 2119/12 (2020.01);
Abstract
A method for optimizing a multi die implementation flow that is aware of mix-and-match die integration for implementing multi-die integrated circuits includes partitioning a netlist into partitions comprehending mix-and-match die integration, wherein each partition will be assigned to a die. Each partition is placed into a corresponding die. A clock tree of the integrated circuit is synthesized. Nets of the integrated circuit in are routed in accordance the placing and synthesizing.