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For the Inventor, By the Inventor

Boise, ID, United States of America

Anand Srinivasan

USPTO Granted Patents = 42 

 

Average Co-Inventor Count = 2.4

ph-index = 13

Forward Citations = 1,477(Granted Patents)


Location History:

  • Boise, ID (US) (1998 - 2011)
  • San Diego, CA (US) (2002 - 2023)

Company Filing History:

goldMedal34 out of 37,905 
 
Micron Technology Incorporated
 patents
silverMedal5 out of 41,326 
 
Qualcomm Incorporated
 patents
bronzeMedal1 out of 59 
 
Micro Technology, Inc.
 patents
4. 2 out of 832,680 
Other
 patents

Years Active: 1998-2025

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42 patents (USPTO):Explore Patents
1. 12230347 - System and memory with configurable metadata portion (2025-02-18),
2. 11728003 - System and memory with configurable error-correction code (ECC) data protection and related methods (2023-08-15),
3. 9575884 - System and method for high performance and low cost flash translation layer (2017-02-21),
4. 8595429 - Wide input/output memory with low density, low latency and high density, high latency blocks (2013-11-26),
5. 8464107 - Surrogate circuit for testing an interface (2013-06-11),
6. 8138039 - Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array (2012-03-20),
7. 7936000 - Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array (2011-05-03),
8. 7642204 - Methods of forming fluorine doped insulating materials (2010-01-05),
9. 7528439 - Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array (2009-05-05),
10. 7374990 - Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array (2008-05-20),
11. 7241655 - Method of fabricating a vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array (2007-07-10),
12. 7112531 - Silicon oxide co-deposition/etching process (2006-09-26),
13. 6952051 - Interlevel dielectric structure (2005-10-04),
14. 6841463 - Interlevel dielectric structure and method of forming same (2005-01-11),
15. 6727190 - Method of forming fluorine doped boron-phosphorous silicate glass (F-BPSG) insulating materials (2004-04-27),

Title: The Innovative Journey of Anand Srinivasan

Introduction:

Anand Srinivasan, a visionary inventor based in Boise, ID, has made significant contributions to the field of technology with his groundbreaking innovations.

Latest Patents:

Anand Srinivasan holds several patents in the areas of artificial intelligence, renewable energy, and sustainable agriculture, showcasing his diverse range of expertise and interests.

Career Highlights:

With a background in engineering and a passion for solving complex problems, Anand has led successful projects that have revolutionized industries and improved the lives of many.

Collaborations:

Throughout his career, Anand Srinivasan has collaborated with leading research institutions, universities, and tech companies to bring his ideas to life and create tangible impact in the world of innovation.

Conclusion:

Anand Srinivasan's relentless pursuit of innovation and his commitment to pushing the boundaries of what is possible make him a true pioneer in the field of technology, inspiring the next generation of inventors to dream big and create change.

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