Micron Technology Incorporated

Qualcomm Incorporated

Other

Micro Technology, Inc.

Anand Srinivasan

Gurtej S Sandhu

Sujit Sharan

Robert James Burke

Ravi T Iyer

Sanh D Tang

Dexter Tamio Chun

Ceredig Roberts

Thomas Arthur Figura

Jungwon Suh

Laurent Rene Moll

Farrell Martin Good

Olivier Alavoine

Raj Narasimhan

Sujit Sharon

Shiqun Gu

Matthew Michael Nowak

Hyunsuk Shin

Christopher Kong Yee Chun

P Venkat Rangan

Mehul Y Shah

Steven Haehnichen

Kamal Bhadada

Indranil Chakraborty

Mohan Mardikar

Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.

System and memory with configurable metadata portion

System and memory with configurable error-correction code (ECC) data protection and related methods

Aspects include systems and methods for increasing performance of a flash translation layer (FTL) of a flash memory device. A copy of FTL tables stored on a flash memory device may be copied to a memory of a host device. The copy of the FTL tables may be directly accessed by the flash memory device to translate between logical addresses provided by the host device for read/write operations from/to a flash memory of the flash memory device, and the respective physical addresses of the flash memory. The flash memory device is granted direct memory access to a portion of the memory of the host device where the copy of the FTL tables is stored. The flash memory device bus masters communication busses connecting the flash memory device to the memory of the host device.

System and method for high performance and low cost flash translation layer

External memory having a high density, high latency memory block; and a low density, low latency memory block. The two memory blocks may be separately accessed by one or more processing functional units. The access may be a direct memory access, or by way of a bus or fabric switch. Through-die vias may connect the external memory to a die comprising the one or more processing functional units.

Wide input/output memory with low density, low latency and high density, high latency blocks

A semiconductor die includes interface logic for performing a function on an external device, and a surrogate circuit in communication with the interface logic. The interface logic facilitates testing of the interface logic by attempting to perform the function on the surrogate circuit. The interface logic may be a memory interface, and the surrogate circuit may be a memory circuit that is a smaller and simpler replica of an external memory die. The surrogate circuit allows the interface logic to be tested before the semiconductor die is physically coupled to the external device, for exampled in a three dimensional (3D) integrated circuit (IC).

Surrogate circuit for testing an interface

A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.

Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array

In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si&#x2014;F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si&#x2014;F bonds onto the substrate from the reactants. In yet another aspect, the invention includes a method of forming a phosphorus-doped silicon oxide having Si&#x2014;F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising triethoxy fluorosilane, a phosphorus-containing precursor, and ozone within the reaction chamber; and c) depositing a phosphorus-doped silicon oxide having Si&#x2014;F bonds onto the substrate from the reactants.

Methods of forming fluorine doped insulating materials

Method of fabricating a vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array

Methods of providing silicon oxide on a substrate in a single process step by simultaneously introducing both a silicon source gas and an etch gas into a CVD chamber. As a result, the method will typically involve simultaneous deposition and etching of the silicon oxide. The method is particularly useful for providing silicon oxide spacers with faceted surfaces.

Silicon oxide co-deposition/etching process

An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.

Interlevel dielectric structure

Interlevel dielectric structure and method of forming same

In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si&mdash;F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si&mdash;F bonds onto the substrate from the reactants. In yet another aspect, the invention includes a method of forming a phosphorus-doped silicon oxide having Si&mdash;F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising triethoxy fluorosilane, a phosphorus-containing precursor, and ozone within the reaction chamber; and c) depositing a phosphorus-doped silicon oxide having Si&mdash;F bonds onto the substrate from the reactants.

Method of forming fluorine doped boron-phosphorous silicate glass (F-BPSG) insulating materials

Growing community of inventors

Boise, ID, United States of America

Anand Srinivasan