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For the Inventor, By the Inventor

Noida, India

Amit Chhabra

This inventor holds 17 USPTO granted patents and 12 published patent applications, primarily in Memory Architecture. Top assignee: Arm Limited. Active years: 2020-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Amit Chhabra. Retrieved from https://idiyas.com/inventor/amit-chhabra-2axv3ngl

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 17 

% Patents Active = 76.5

Average Co-Inventor Count = 2.2

ph-index = 1

Forward Citations = 6(Granted Patents)


Company Filing History:

goldMedal17 out of 3,786 
 
Arm Limited
 patents

Years Active: 2020-2026

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Areas of Expertise:
Droop Protection
Power Management
Voltage Detection
Multi-Dimensional Structure
Bitcell Architecture
Memory Read Characteristics
Transient Sensing
Fault Detection
Voltage Retention
Stacked Transistors
Adaptive Voltage Scaling
Ring Oscillator
17 patents (USPTO):Explore Patents
1. 12732171 - Droop protection method and circuit (2026-09-08),
2. 12719278 - Method and system for power management (2026-08-25),
3. 12681056 - Voltage droop detection (2026-07-14),
4. 12599036 - Circuit architecture in multi-dimensional monolithic structure (2026-04-07),
5. 12165737 - Multi-bitcell structure with shared read port (2024-12-10),
6. 12052860 - Memory architecture (2024-07-30),
7. 12040232 - Multi-transistor stack architecture in a single vertical stack (2024-07-16),
8. 12035517 - Multi-transistor stack bitcell architecture (2024-07-09),
9. 11895816 - Bitcell architecture (2024-02-06),
10. 11742051 - Sensor for performance variation of memory read and write characteristics (2023-08-29),
11. 11495499 - Method of forming multi-stack transistors in a single semiconductor die (2022-11-08),
12. 11114154 - Voltage retention techniques (2021-09-07),
13. 11069424 - Sensor for performance variation of memory read and write characteristics (2021-07-20),
14. 10964379 - Ring oscillator based bitcell delay monitor (2021-03-30),
15. 10848186 - Fault detection circuitry (2020-11-24),

Title: The Innovative Mind of Amit Chhabra

Introduction

Amit Chhabra is a prominent inventor based in Noida, India, known for his significant contributions to the field of technology. With a total of 13 patents to his name, he has made remarkable strides in the development of advanced memory architectures and multi-bitcell structures. His work reflects a deep understanding of electronic devices and their functionalities.

Latest Patents

Among his latest patents, Amit has developed a multi-bitcell structure with a shared read port. This innovation involves a device featuring multiple bitcells, which include first port transistors arranged in a P-over-N stack configuration and second port transistors in an N-over-N stack configuration. Additionally, he has worked on a memory architecture that utilizes a multi-transistor logic structure. This structure can incorporate pairs of P-type transistors in a P-over-P multi-transistor stack or pairs of N-type transistors in an N-over-N multi-transistor stack, showcasing his versatility in design.

Career Highlights

Amit Chhabra is currently employed at Arm Limited, a leading company in semiconductor and software design. His role at Arm Limited allows him to leverage his expertise in creating innovative solutions that enhance memory performance and efficiency. His contributions have been instrumental in advancing the company's technological capabilities.

Collaborations

Throughout his career, Amit has collaborated with notable professionals in the industry, including Rainer

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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