Arm Limited

Amit Chhabra

David Victor Pietromonaco

Rainer Herberholz

George McNeil Lattimore

Brian Tracy Cline

Vivek Asthana

Jitendra Dasani

Yannis Jallamion-Grive

Saikat Kumar Banik

Shanuj Garg

Various implementations described herein are directed to a device having a multi-bitcell structure with multiple bitcells. The multiple bitcells may include first port transistors and second port transistors. The first port transistors may be arranged in a P-over-N stack configuration, and the second port transistors may be arranged in an N-over-N stack configuration.

Multi-bitcell structure with shared read port

Various implementations described herein relate to a device with a multi-transistor logic structure for use in memory architecture. In some applications, the multi-transistor logic structure may have a pair of P-type transistors that are arranged in a P-over-P multi-transistor stack. In other applications, the multi-transistor logic structure may have a pair of N-type transistors that are arranged in an N-over-N multi-transistor stack.

Memory architecture

Various implementations described herein relate to a method for manufacturing, or causing to be manufactured, multiple devices packaged within a single semiconductor die. The multiple devices may have first devices that are arranged in a first multi-transistor stack with a first P-N configuration. The multiple devices may have second devices that are arranged in a second multi-transistor stack with a second P-N configuration that is different than the first P-N configuration.

Multi-transistor stack architecture in a single vertical stack

Various implementations described herein are related to a device having multiple transistors in a single stack arranged as a cross-coupled bitcell latch. Also, the multiple transistors may be disposed in a multi-transistor stack configuration that is formed within a single monolithic semiconductor die. In some implementations, the multiple transistors may be arranged as a bitcell for single-port memory applications.

Multi-transistor stack bitcell architecture

Various implementations described herein are related to a device having multiple transistors that are arranged as a bitcell. The multiple transistors may include multiple P-type transistors that are arranged in a P-over-P stack configuration, and the multiple transistors may include multiple N-type transistors that are arranged in an N-over-N stack configuration.

Bitcell architecture

Various implementations described herein refer to an integrated circuit having a first memory structure and a second memory structure. The first memory structure is disposed in a first area of the integrated circuit, and the first memory structure has first memory cells with first transistors. The second memory structure is disposed in a second area of the integrated circuit that is different than the first area, and the second memory structure has second memory cells with second transistors that are separate from the first transistors. The second transistors of the second memory cells are arranged to provide an output oscillating frequency for detecting variation of performance of the first transistors of the first memory cells.

Sensor for performance variation of memory read and write characteristics

Method of forming multi-stack transistors in a single semiconductor die

Various implementations described herein are directed to a device having voltage generator circuitry that provides a temperature-compensated voltage. The device may include amplifier circuitry that receives the temperature-compensated voltage from the voltage generator circuitry and provides an output voltage based on the temperature-compensated voltage. The device may include voltage retention circuitry that receives the output voltage from the amplifier circuitry and provides a retention voltage to memory based on the output voltage.

Voltage retention techniques

Various implementations described herein refer to an integrated circuit having a row of bitcells that are chained together in series to operate as a ring oscillator. Each bitcell in the row of bitcells has multiple transistors that are independent of additional transistors to form the ring oscillator. The multiple transistors of each bitcell in the row of bitcells are arranged to function as an inverter.

Ring oscillator based bitcell delay monitor

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include first decoding circuitry that receives an address and partially decodes the address to generate a partially decoded address. The integrated circuit may include second decoding circuitry that receives the partially decoded address, generates a decoded address, and provides the decoded address to a wordline. The integrated circuit may include encoding circuitry that receives the decoded address from the wordline and encodes the decoded address to generate an encoded address. The integrated circuit may include comparing circuitry that receives the encoded address and compares the encoded address with the address to detect faults in the memory circuitry.

Fault detection circuitry

Various implementations described herein are directed to an integrated circuit that has memory circuitry with a memory structure and a reference path. The integrated circuit includes performance sensing circuitry having a logic structure that is adapted to detect variation of performance of the memory structure. The integrated circuit includes power management circuitry that is coupled to the memory circuitry and the performance sensing circuitry. The power management circuitry receives a feedback signal from the performance sensing circuitry and adaptively adjusts voltage provided to the memory circuitry based on the feedback signal to affect performance of the memory structure. The memory circuitry has a logic stage that reduces signal delay in the reference path for alignment with the adaptively adjusted voltage.

Self-timed memory with adaptive voltage scaling

Various implementations described herein are directed to an integrated circuit with logic circuitry having one or more components. The integrated circuit may include performance sensing circuitry that provides a performance sensing output associated with detecting variation of switching delays of the one or more components forming the logic circuitry. The integrated circuit may include transient sensing circuitry that receives the performance sensing output and provides a transient sensing output for determining stability of operating conditions of the performance sensing circuitry during one or more sampling periods. The transient sensing circuitry may use a finite state machine (FSM) to sense and classify changes in temporal behavior of the transient sensing output.

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Noida, India

Amit Chhabra