The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 2024
Filed:
Jan. 14, 2021
Applicant:
Arm Limited, Cambridge, GB;
Inventors:
Amit Chhabra, Noida, IN;
David Victor Pietromonaco, Cupertino, CA (US);
Assignee:
Arm Limited, Cambridge, GB;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H10B 20/00 (2023.01);
U.S. Cl.
CPC ...
H10B 20/60 (2023.02); G11C 7/065 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); H01L 27/0922 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01);
Abstract
Various implementations described herein relate to a device with a multi-transistor logic structure for use in memory architecture. In some applications, the multi-transistor logic structure may have a pair of P-type transistors that are arranged in a P-over-P multi-transistor stack. In other applications, the multi-transistor logic structure may have a pair of N-type transistors that are arranged in an N-over-N multi-transistor stack.