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For the Inventor, By the Inventor

San Jose, CA, United States of America

Alexandre Andreev

This inventor holds 20 USPTO granted patents. Top assignees: Lsi Corporation, Lsi Logic Corporation. Active years: 2004-2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Alexandre Andreev. Retrieved from https://idiyas.com/inventor/alexandre-andreev

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 20

% Patents Active = 25.0

Average Co-Inventor Count = 3.3

ph-index = 5

Forward Citations = 259(Granted Patents)


Company Filing History:

goldMedal14 out of 2,353 
 
Lsi Corporation
 patents
silverMedal6 out of 3,715 
 
Lsi Logic Corporation
 patents

Years Active: 2004-2013

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20 patents (USPTO):Explore Patents
1. 8566769 - Method and apparatus for generating memory models and timing database (2013-10-22),
2. 8312072 - Universal Galois field multiplier (2012-11-13),
3. 8245168 - Method and apparatus for generating memory models and timing database (2012-08-14),
4. 8209589 - Reed-solomon decoder with a variable number of correctable errors (2012-06-26),
5. 8176397 - Variable redundancy reed-solomon encoder (2012-05-08),
6. 8156391 - Data controlling in the MBIST chain architecture (2012-04-10),
7. 8046643 - Transport subsystem for an MBIST chain architecture (2011-10-25),
8. 8037432 - Method and apparatus for mapping design memories to integrated circuit layout (2011-10-11),
9. 7949909 - Address controlling in the MBIST chain architecture (2011-05-24),
10. 7788563 - Generation of test sequences during memory built-in self testing of multiple memories (2010-08-31),
11. 7584442 - Method and apparatus for generating memory models and timing database (2009-09-01),
12. 7424687 - Method and apparatus for mapping design memories to integrated circuit layout (2008-09-09),
13. 7389484 - Method and apparatus for tiling memories in integrated circuit layout (2008-06-17),
14. 7308633 - Master controller architecture (2007-12-11),
15. 7207026 - Memory tiling architecture (2007-04-17),

Title: Innovations and Contributions of Alexandre Andreev in San Jose, CA

Introduction

Alexandre Andreev, based in San Jose, California, is a recognized inventor with a remarkable portfolio of 20 patents. His work primarily focuses on advanced technologies in memory systems and digital circuits, contributing significantly to the field of electronics.

Latest Patents

Among Alexandre's latest patents is a "Method and Apparatus for Generating Memory Models and Timing Database." This innovation involves utilizing a memory timing database to define a range of characterization memories that can be mapped to a memory resource, each having unique memory parameters. Furthermore, it details various tiling variants for each characterization memory, with timing characteristics stored for efficient resource management.

Another pivotal patent is the "Universal Galois Field Multiplier," which encompasses an apparatus designed with a multiplier circuit and a multiplexing circuit. The multiplier is adept at multiplying two numbers using a programmable base value and generating multiple intermediate results, showcasing the complexity and efficiency of his inventions.

Career Highlights

Throughout his career, Alexandre has made significant strides in the tech industry, notably working for companies such as LSI Corporation and LSI Logic Corporation. His experiences at these organizations have bolstered his expertise, enabling him to develop groundbreaking technologies that address complex engineering challenges.

Collaborations

Alexandre has collaborated with several notable professionals, including Ranko L. Scepanovic and Andrey Nikitin. These partnerships have been instrumental in driving forward innovative projects and enhancing the depth of research in their respective fields.

Conclusion

Alexandre Andreev's contributions to the field of electronics through his patents and collaborations illustrate his pivotal role as an inventor. His innovative technologies continue to pave the way for advancements in memory systems and digital circuits, establishing him as a prominent figure in the realm of innovation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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