The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7389484 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 17, 2008

Filed:

Nov. 16, 2005
Applicants:

Alexandre Andreev, San Jose, CA (US);

Andrey Nikitin, Moscow, RU;

Ilya V. Neznanov, Moscow, RU;

Ranko Scepanovic, Saratoga, CA (US);

Inventors:

Alexandre Andreev, San Jose, CA (US);

Andrey Nikitin, Moscow, RU;

Ilya V. Neznanov, Moscow, RU;

Ranko Scepanovic, Saratoga, CA (US);

Assignee:

LSI Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A process and apparatus are provided for tiling objects, such as design memories, in one or more respective object locations in a layout pattern. For each object, the following steps are performed recursively based on a comparison of at least one of a capacity and a width of the object and that of the respective object location: (1) do nothing; (2) reconfigure the object to have a different capacity and/or width; and (3) split the object into two or more separate objects. The recursion is repeated for each reconfigured object and each separated object.


Find Patent Forward Citations

Andreev, Alexandre. (2008). Method and apparatus for tiling memories in integrated circuit layout (U.S. Patent No. 7389484). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7389484

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