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San Francisco, CA, United States of America

Aaron Paul Hurst

This inventor holds 6 USPTO granted patents. Top assignee: Cadence Design Systems, Inc.. Active years: 2013-2016.

USPTO Granted Patents = 6

% Patents Active = 100.0

Average Co-Inventor Count = 1.5

ph-index = 5

Forward Citations = 90(Granted Patents)

Location History:

Berkeley, CA (US) (2013)
San Francisco, CA (US) (2013 - 2016)

Company Filing History:

Cadence Design Systems, Inc.

Years Active: 2013-2016

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6 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9411912 - Clock topology planning for reduced power consumption (2016-08-09),

2. 9280614 - Methods, systems, and apparatus for clock topology planning with reduced power consumption (2016-03-08),

3. 9135375 - Methods for construction and optimization of a clock tree plan for reduced power consumption (2015-09-15),

4. 8826211 - Graphical user interface for physically aware clock tree planning (2014-09-02),

5. 8438511 - Minimal logic duplication for preserving reset behavior post-retiming (2013-05-07),

6. 8423939 - Boundary buffers to model register incompatibility during pre-retiming optimization (2013-04-16),

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