The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 2013
Filed:
Dec. 30, 2009
Aaron Hurst, Berkeley, CA (US);
Aaron Hurst, Berkeley, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Methods, systems, and devices for logic synthesis that preserve a reset behavior of a circuit are provided. A method for logic synthesis may include providing the circuit. A memory element may be identified at a first location within the circuit, where the memory element is reset with a first reset value. The memory element may be relocated across a first portion of the circuit resulting in a one relocated memory element. The relocated memory element may be duplicated. The relocated memory element and the duplicated memory element may be connected with the circuit. Multiple reset values for the relocated memory element and the duplicated memory element may be determined, where the first reset value is produced at the first location when the multiple reset values are propagated through the circuit from the relocated memory element and the duplicated memory element to the first location.